NCP5422A, NCP5423

http://onsemi.com

8

0.40 V PWM comparator offset threshold and the artificial

ramp, the PWM comparator terminates the initial pulse.

Figure 4. Idealized Waveforms

8.6 V

0.45 V

GATE(H)1

GATE(H)2

UVLO

STARTUP

NORMAL OPERATION

Normal Operation

During normal operation, the duty cycle of the gate drivers

maintains the regulated output voltage under steady state

conditions. Variations in supply line or output load

conditions will result in changes in duty cycle to maintain

regulation.

Gate Charge Effect on Switching Times

When using the onboard gate drivers, the gate charge has

an important effect on the switching times of the FETs. A

finite amount of time is required to charge the effective

capacitor seen at the gate of the FET. Therefore, the rise and

fall times rise linearly with increased capacitive loading,

according to the following graphs.

Figure 5. Average Rise and Fall Times

90

80

70

60

50

40

30

20

10

0

0

1

23

4

5

67

8

Load (nF)

Average Fall Time

Average Rise Time

Transient Response

The 150 ns reaction time of the control loop provides fast

transient response to any variations in input voltage and

output current. Pulse−by−pulse adjustment of duty cycle is

provided to quickly ramp the inductor current to the required

level. Since the inductor current cannot be changed

instantaneously, regulation is maintained by the output

capacitors during the time required to slew the inductor

current. For better transient response, several high

frequency and bulk output capacitors are usually used.

Out−of−Phase Synchronization

In out−of−phase synchronization, the turn−on of the

second channel is delayed by half the switching cycle. This

delay is supervised by the oscillator, which supplies a clock

signal to the second channel which is 180

° out of phase with

the clock signal of the first channel.

The advantages of out−of−phase synchronization are

many. Since the input current pulses are interleaved with one

another, the overlap time is reduced. The effect of this

overlap reduction is to reduce the input filter requirement,

allowing the use of smaller components. In addition, since

peak current occurs during a shorter time period, emitted

EMI

is

also

reduced,

thereby

reducing

shielding

requirements.

Overvoltage Protection

Overvoltage Protection (OVP) is provided as a result of

no additional external components. The control loop

responds to an overvoltage condition within 150 ns, turning

off the upper MOSFET and disconnecting the regulator

from its input voltage. This results in a crowbar action to

clamp the output voltage preventing damage to the load. The

regulator remains in this state until the overvoltage

condition ceases.

Hiccup Overcurrent Protection

A lossless hiccup mode short circuit protection feature is

provided on the chip. The only external component required

is the COMP1 capacitor. Any overcurrent condition results

in the immediate shutdown of both output phases. Both the

upper and lower gate drives are driven low, turning off both

MOSFETs.

A comparator between the IS+ and IS− on each output

phase detects a short circuit when the voltage difference

between the two pins exceeds 70 mV and sets the fault latch.

The fault latch immediately turns off the error amplifier and

discharges both COMP capacitors. The capacitor connected

to COMP1 is discharged through a 5.0

mA current sink in

order to provide timing for the reset cycle. When COMP1

has fallen below 0.25 V, a comparator resets the fault latch

and error amplifier 1 begins to charge COMP1 with a 30

mA

source current. When COMP1 exceeds the feedback voltage

plus the PWM Comparator offset voltage, the normal

switching cycle will resume.

If the short circuit condition persists through the restart

cycle, the overcurrent reset cycle will repeat itself until the

short circuit is removed, resulting in small hiccup output

pulses while the COMP capacitor charges, as shown in

Figure 6.