NCP5424DR2 datasheet(9/18 Pages) ONSEMI

Part #	NCP5424DR2

Description	Dual Synchronous Buck Controller with Input Current Sharing

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Manufacturer	ONSEMI [ON Semiconductor]

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NCP5424

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9

Out−of−Phase Synchronization

In out−of−phase synchronization, the turn−on of the

second channel is delayed by half the switching cycle. This

delay is supervised by the oscillator, which supplies a clock

signal to the second channel which is 180

° out of phase with

the clock signal of the first channel.

The advantages of out−of−phase synchronization are

many. Since the input current pulses are interleaved with one

another, the overlap time is reduced. The effect of this

overlap reduction is to reduce the input filter requirement,

allowing the use of smaller components. In addition, since

peak current occurs during a shorter time period, emitted

EMI

is

also

reduced,

thereby

reducing

shielding

requirements.

Overvoltage Protection

Overvoltage Protection (OVP) is provided as a result of

the normal operation of the V2 control method and requires

no additional external components. The control loop

responds to an overvoltage condition within 150 ns, turning

off the upper MOSFET and disconnecting the regulator

from its input voltage. This results in a crowbar action to

clamp the output voltage preventing damage to the load. The

regulator remains in this state until the overvoltage

condition ceases.

Input Current Sharing

In contemporary high−end applications, part of a system

may require more power than is available from one supply.

The NCP5424 dual controller can address this requirement

in two ways.

In many cases, it is sufficient to be able to set the input

power sharing as a ratio so that one source always supplies

a certain percentage of the total. This is achieved by having

the Error Amplifier inputs from Slave side, Controller Two,

brought to external pins so its’ reference is available.

Current information from the Master, Controller One,

provides a reference for the Slave. Current information from

the Slave is fed back to the error amplifier’s inverting input.

The Slave will try to adjust its current to match the current

information fed to its reference input from the Master. If this

information is

1/2 the voltage developed across the Master’s

output inductor, the Slave will run at half current and supply

a percentage, nominally 33% in this case, of the total current.

In other applications however, the user may not only wish

to draw a percentage of power from one source, but also may

need to limit the power drawn from that source. The Slave

has a Cycle−By−Cycle current limit. In this case, the Slave

can be programmed to budget the maximum input power.

For example, a designer may wish to draw equal amounts of

power from two 5−volt sources, but only 2 amps are

available from one of the supplies. In this case, the dual

controller will draw equally from the two sources up to a

total of 4 amps. At this point, the Slave controller goes into

current limit and draws no more than its preset budget. The

Master continues to supply the remaining output current up

to the maximum that the application requires.

Current Limiting

The NCP5424 employs two types of current limits.

Controller One has a Hiccup Mode Current Limit and

Controller Two has Cycle−By−Cycle current limit. Any

overcurrent condition on Controller One results in the

immediate shutdown of both output phases. In a dual output

application, independent current limits are not supported.

The NCP5424 has two current limiting amplifiers that

have a built in 70 mV offset. These differential amplifiers

have a common mode range from zero to 5.5 volts and low

input current. They share a common negative input that in

single output voltage application is not a limitation.

However in dual output applications independent current

limits are not supported.

Once a voltage greater than 70 mV is applied to the current

limiting amplifier of Controller 2; it produces an output that,

as shown in the block diagram, resets the output RS flip flop.

This ends the PWM pulse for the particular cycle and in so

doing, limits the energy delivered to the load on a

cycle−by−cyclebasis. One advantage of this current limiting

scheme is that the NCP5424 will limit transient currents and

will resume normal operation the cycle after the transient

goes away.

A second benefit is that this action of limiting the PWM

pulse width means that in an input power sharing

application, one controller can be current limiting while the

other supplies the remaining current needs.

The fault latch immediately turns off the error amplifier

and discharges both COMP capacitors. The capacitor

connected to COMP1 is discharged through a 5.0

mA current

sink in order to provide timing for the reset cycle. When

COMP1 has fallen below 0.25 V, a comparator resets the

fault latch and error amplifier 1 begins to charge COMP1

with a 30

mA source current. When COMP1 exceeds the

feedback voltage plus the PWM Comparator offset voltage,

the normal switching cycle will resume. If the short circuit

condition persists through the restart cycle, the overcurrent

reset cycle will repeat itself until the short circuit is removed,

resulting in small “hiccup” output pulses while the COMP

capacitor charges and discharges. Please see the section

titled “Current Sharing Compensation Capacitor Selection”

for proper Comp capacitor selection.

Cycle−By−Cycle current limit controls the amount of

current available from Controller 2. Controller 2 has a

current limiting comparator that, by truncating the

respective controller’s PWM pulse width, limits the

available current on a pulse−by−pulse basis. This

comparator has a built in 70 mV offset that provides a

reference for setting current limit.

Output Enable

On/Off control of the regulator outputs can be

implemented by pulling the COMP pins low. The COMP

pins must be driven below the 0.40 V PWM comparator

offset voltage in order to disable the switching of the GATE

drivers.

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