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NCV2002SN2T1 Datasheet(PDF) 10 Page - ON Semiconductor |
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NCV2002SN2T1 Datasheet(HTML) 10 Page - ON Semiconductor |
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10 / 16 page  NCS2002, NCV2002 http://onsemi.com 10 0 ±0.5 VS, SUPPLY VOLTAGE (V) ±1.0 ±1.5 ±2.0 ±2.5 4.0 6.0 0 2.0 8.0 10 Figure 32. Propagation Delay versus Supply Voltage RL = 10 k TA = 25°C ±3.0 ±3.5 12 14 16 ton toff APPLICATION INFORMATION AND OPERATING DESCRIPTION GENERAL INFORMATION The NCS2002 is an industry first rail−to−rail input, rail−to−rail output amplifier that features guaranteed sub one volt operation. This unique feature set is achieved with the use of a modified analog CMOS process that allows the implementation of depletion MOSFET devices. The amplifier has a 1.0 MHz gain bandwidth product, 1.2 V/ ms slew rate and is operational over a power supply range less than 0.9 V to as high as 7.0 V. Inputs The input topology chosen for this device series is unconventional when compared to most low voltage operational amplifiers. It consists of an N−channel depletion mode differential transistor pair that drives a folded cascade stage and current mirror. This configuration extends the input common mode voltage range to encompass the VEE and VCC power supply rails, even when powered from a combined total of less than 0.9 volts. Figures 27, 28 and 29 show the input common mode voltage range versus power supply voltage. The differential input stage is laser trimmed in order to minimize offset voltage. The N−channel depletion mode MOSFET input stage exhibits an extremely low input bias current of less than 10 pA. The input bias current versus temperature is shown in Figure 4. Either one or both inputs can be biased as low as VEE minus 300 mV to as high as 7.0 V without causing damage to the device. If the input common mode voltage range is exceeded, the output will not display a phase reversal. If the maximum input positive or negative voltage ratings are to be exceeded, a series resistor must be used to limit the input current to less than 2.0 mA. The ultra low input bias current of the NCS2002 allows the use of extremely high value source and feedback resistor without reducing the amplifier’s gain accuracy. These high value resistors, in conjunction with the device input and printed circuit board parasitic capacitances Cin, will add an additional pole to the single pole amplifier in Figure 33. If low enough in frequency, this additional pole can reduce the phase margin and significantly increase the output settling time. The effects of Cin, can be canceled by placing a zero into the feedback loop. This is accomplished with the addition of capacitor Cfb. An approximate value for Cfb can be calculated by: Cfb + Rin Cin Rfb Figure 33. Input Capacitance Pole Cancellation + − Output Rfb Cin Rin Cfb Cin = Input and printed circuit board capacitance Input |
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