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NCV4274DS50G Datasheet(PDF) 2 Page - ON Semiconductor |
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NCV4274DS50G Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 16 page NCV4274, NCV4274A http://onsemi.com 2 Figure 1. Block Diagram − + Bandgap Refernece Thermal Shutdown Current Limit and Saturation Sense GND Q I Pin Definitions and Functions Pin No. Symbol Function 1 I Input; Bypass directly at the IC a ceramic capacitor to GND. 2,4 GND Ground 3 Q Output; Bypass with a capacitor to GND. 1. DPAK 3LD package code 6025 2. D2PAK 3LD package code 6083 ABSOLUTE MAXIMUM RATINGS Pin Symbol, Parameter Symbol Condition Min Max Unit I, Input−to−Regulator Voltage VI −42 45 V Current II Internally Limited Internally Limited I, Input peak Transient Voltage to Regulator with Respect to GND VI 60 V Q, Regulated Output Voltage VQ −1.0 40 V Current IQ Internally Limited Internally Limited GND, Ground Current IGND − 100 mA Junction Temperature Storage Temperature TJ TStg − −50 150 150 °C °C ESD Capability, Human Body Model ESDHB 4 kV ESD Capability, Machine Model ESDMM 200 V ESD Capability, Charged Device Model ESDCDM 1 kV Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. This device series incorporates ESD protection and is tested by the following methods: ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A114) ESD MM tested per AEC−Q100−003 (EIA/JESD22−A115) ESD CDM tested per EIA/JES D22/C101, Field Induced Charge Model |
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