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AT45D041A-JI Datasheet(PDF) 6 Page - ATMEL Corporation |
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AT45D041A-JI Datasheet(HTML) 6 Page - ATMEL Corporation |
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6 / 28 page  AT45D041A 6 MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations. Data is first shifted into buffer 1 or buffer 2 from the SI pin and then programmed into a specified page in the main memory. To initiate the operation, an 8-bit opcode, 82H for buffer 1 or 85H for buffer 2, must be fol- lowed by the four reserved bits and 20 address bits. The 11 most significant address bits (PA10-PA0) select the page in the main memory where data is to be written, and the next nine address bits (BFA8-BFA0) select the first byte in the buffer to be written. After all address bits are shifted in, the part will take data from the SI pin and store it in one of the data buffers. If the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. When there is a low-to-high transition on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. Both the erase and the program- ming of the page are internally self timed and should take place in a maximum of time tEP. During this time, the status register will indicate that the part is busy. Additional Commands MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start the operation, an 8-bit opcode, 53H for buffer 1 and 55H for buffer 2, must be followed by the four reserved bits, 11 address bits (PA10-PA0) which specify the page in main memory that is to be transferred, and nine don’t care bits. The CS pin must be low while tog- gling the SCK pin to load the opcode, the address bits, and the don’t care bits from the SI pin. The transfer of the page of data from the main memory to the buffer will begin when the CS pin transitions from a low to a high state. During the transfer of a page of data (tXFR), the status register can be read to determine whether the transfer has been completed or not. MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can be compared to the data in buffer 1 or buffer 2. To initiate the operation, an 8-bit opcode, 60H for buffer 1 and 61H for buffer 2, must be fol- lowed by 24 address bits consisting of the four reserved bits, 11 address bits (PA10-PA0) which specify the page in the main memory that is to be compared to the buffer, and nine don’t care bits. The CS pin must be low while toggling the SCK pin to load the opcode, the address bits, and the don’t care bits from the SI pin. On the low-to-high transition of the CS pin, the 264 bytes in the selected main memory page will be compared with the 264 bytes in buffer 1 or buffer 2. During this time (tXFR), the status register will indi- cate that the part is busy. On completion of the compare operation, bit 6 of the status register is updated with the result of the compare. AUTO PAGE REWRITE: This mode is only needed if multi- ple bytes within a page or multiple pages of data are modified in a random fashion. This mode is a combination of two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-in Erase. A page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed back into its original page of main memory. To start the rewrite opera- tion, an 8-bit opcode, 58H for buffer 1 or 59H for buffer 2, must be followed by the four reserved bits, 11 address bits (PA10-PA0) that specify the page in main memory to be rewritten, and nine additional don’t care bits. When a low- to-high transition occurs on the CS pin, the part will first transfer data from the page in main memory to a buffer and then program the data from the buffer back into same page Block Erase Addressing PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Block 0 0 00 00 00 X X X 0 0 0 00 00 01 X X X 1 0 0 00 00 10 X X X 2 0 0 00 00 11 X X X 3 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 1 1 11 11 00 X X X 252 1 1 11 11 01 X X X 253 1 1 11 11 10 X X X 254 1 1 11 11 11 X X X 255 |
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