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ATTINY13-20PU Datasheet(PDF) 9 Page - ATMEL Corporation |
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ATTINY13-20PU Datasheet(HTML) 9 Page - ATMEL Corporation |
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9 / 177 page  9 ATtiny13 2535G–AVR–01/07 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. Figure 5. The X-, Y-, and Z-registers In the different addressing modes these address registers have functions as fixed dis- placement, automatic increment, and automatic decrement (see the instruction set reference for details). Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Regis- ter always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Inter- rupt Stacks are located. This Stack space in the data SRAM is automaticall defined to the last address in SRAM during power on reset. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incre- mented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The num- ber of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 15 XH XL 0 X-register 70 7 0 R27 (0x1B) R26 (0x1A) 15 YH YL 0 Y-register 70 7 0 R29 (0x1D) R28 (0x1C) 15 ZH ZL 0 Z-register 70 7 0 R31 (0x1F) R30 (0x1E) Bit 151413 121110 9 8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 765 432 10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 0 0 1 1 1 1 1 |
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