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AT25040A-10TU-1.8 Datasheet(PDF) 1 Page - ATMEL Corporation

Part # AT25040A-10TU-1.8
Description  SPI Serial EEPROM
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT25040A-10TU-1.8 Datasheet(HTML) 1 Page - ATMEL Corporation

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3348J–SEEPR–8/06
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
– Data Sheet Describes Mode 0 Operation
Low-voltage and Standard-voltage Operation
– 2.7 (V
CC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
20 MHz Clock Rate (5V)
8-byte Page Mode
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
Self-timed Write Cycle (5 ms max)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
Automotive Devices Available
8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3) and 8-
lead TSSOP Packages
Die Sales: Wafer Form, Waffle Pack, Bumped Wafers
Description
The AT25010A/020A/040A provides 1024/2048/4096 bits of serial electrically eras-
able programmable read-only memory (EEPROM) organized as 128/256/512 words of
8 bits each. The device is optimized for use in many industrial and commercial appli-
cation s wh ere low-power an d low-vo lta ge op er ation a re esse ntial. The
AT25010A/020A/040A is available in space saving 8-lead PDIP, 8-lead JEDEC SOIC,
8-lead Ultra Thin mini-MAP (MLP 2x3), and 8-lead TSSOP packages.
The AT25010A/020A/040A is enabled through the Chip Select pin (CS) and accessed
via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO),
and Serial Clock (SCK). All programming cycles are completely self-timed, and no
separate erase cycle is required before write.
Block write protection is enabled by programming the status register with one of four
blocks of write protection. Separate Program Enable and Program disable instructions
are provided for additional data protection. Hardware data protection is provided via
the WP pin to protect against inadvertent write attempts. The HOLD pin may be used
to suspend any serial communication without resetting the serial sequence.
Table 1. Pin Configuration
Pin Name
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
SPI Serial
EEPROM
1K (128x8)
2K (256x8)
4K (512x8)
AT25010A
AT25020A
AT25040A
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
CS
SO
WP
GN D
VC C
HO L
SC K
SI
1
2
3
4
8
7
6
5
CS
SO
WP
GN D
VC C
HO L
SC K
SI
8-lead PDIP
8-lead SOIC
8-lead TSSOP
8-lead Ultra Thin mini-MAP (MLP 2x3)
Bottom view


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