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AT89LP4052 Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT89LP4052 Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 90 page  7 3547F–MICRO–6/06 AT89LP2052/LP4052 7. Comparison to Standard 8051 The AT89LP2052/LP4052 is part of a family of devices with enhanced features that are fully binary compatible with the MCS-51 instruction set. In addition, most SFR addresses, bit assign- ments, and pin alternate functions are identical to Atmel's existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are differ- ent from those of Atmel's standard 8051 products such as AT89S52 or AT89S2051. The differences from the standard 8051 are outlined in the following paragraphs. 7.1 System Clock The CPU clock frequency equals the external XTAL1 frequency. The oscillator is no longer divided by 2 to provide the internal clock, and x2 mode is not supported. 7.2 Instruction Execution with Single-cycle Fetch The CPU fetches one code byte from memory every clock cycle instead of every six clock cycles. This greatly increases the throughput of the CPU. As a consequence, the CPU no longer executes instructions in 12 to 48 clock cycles. Each instruction executes in only 1 to 4 clock cycles. See Section 21. “Instruction Set Summary” on page 49 for more details. 7.3 Interrupt Handling The interrupt controller polls the interrupt flags during the last clock cycle of any instruction. In order for an interrupt to be serviced at the end of an instruction, its flag needs to have been latched as active during the next to last clock cycle of the instruction, or in the last clock cycle of the previous instruction if the current instruction executes in only a single clock cycle. 7.4 Timer/Counters The Timer/Counters increment at a rate of once per clock cycle. This compares to once every 12 clocks in the standard 8051. 7.5 Serial Port The baud rate of the UART in Mode 0 is 1/2 the clock frequency, compared to 1/12 the clock fre- quency in the standard 8051. In should also be noted that when using Timer 1 to generate the baud rate in Mode 1 or Mode 3, the timer counts at the clock frequency and not at 1/12 the clock frequency. To maintain the same baud rate in the AT89LP2052/LP4052 while running at the same frequency as a standard 8051, the time-out period must be 12 times longer. Mode 1 of Timer 1 supports 16-bit auto-reload to facilitate longer time-out periods for generating low baud rates. 7.6 Watchdog Timer The Watchdog Timer in AT89LP2052/LP4052 counts at a rate of once per clock cycle. This compares to once every 12 clocks in the standard 8051. |
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