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AT25256AY4-10YU-1.8 Datasheet(PDF) 1 Page - ATMEL Corporation |
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AT25256AY4-10YU-1.8 Datasheet(HTML) 1 Page - ATMEL Corporation |
1 / 21 page 1 1 2 3 4 8 7 6 5 CS SO WP GND VCC HOLD SCK SI 8-lead PDIP 1 2 3 4 8 7 6 5 CS SO WP GND VCC HOLD SCK SI 8-lead SOIC 1 2 3 4 8 7 6 5 CS SO WP GND VCC HOLD SCK SI 8-lead TSSOP 1 2 3 4 8 7 6 5 VCC HOLD SCK SI CS SO WP GND 8-lead SAP VCC HOLD SCK S I CS SO WP GND 1 2 3 4 8 7 6 5 8-ball dBGA2 Bottom View Bottom View Features • Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) • Data Sheet Describes Mode 0 Operation • Low-voltage and Standard-voltage Operation – 2.7 (V CC = 2.7V to 5.5V) – 1.8 (V CC = 1.8V to 5.5V) • 20 MHz Clock Rate (5V) • 64-byte Page Mode and Byte Write Operation • Block Write Protection – Protect 1/4, 1/2, or Entire Array • Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection • Self-timed Write Cycle (5 ms Max) • High-reliability – Endurance: 1 Million Write Cycles – Data Retention: >100 Years • Automotive Grade, Extended Temperature and Lead-free/Halogen-free Devices Available • 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-ball dBGA2 and 8-lead SAP Packages • Die Sales: Wafer Form, Waffle Pack, and Bumped Die Description The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial appli- cations where low-power and low-voltage operation are essential. The devices are available in space saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8- lead TSSOP, 8-ball dBGA2 and 8-lead SAP packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions. The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa- rate Erase cycle is required before Write. Table 1. Pin Configurations Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect HOLD Suspends Serial Input NC No Connect 3368H–SEEPR–8/05 SPI Serial EEPROMs 128K (16,384 x 8) 256K (32,768 x 8) AT25128A AT25256A |
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