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T89C5115-RATIM Datasheet(PDF) 8 Page - ATMEL Corporation |
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T89C5115-RATIM Datasheet(HTML) 8 Page - ATMEL Corporation |
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8 / 113 page  8 AT89C5115 4128F–8051–05/06 Read-Modify-Write Instructions Some instructions read the latch data rather than the pin data. The latch based instruc- tions read the data, modify the data and then rewrite the latch. These are called ’Read- Modify-Write’ instructions. Below is a complete list of these special instructions (See Table 1). When the destination operand is a Port or a Port bit, these instructions read the latch rather than the pin: It is not obvious that the last three instructions in this list are Read-Modify-Write instruc- tions. These instructions read the port (all 8 bits), modify the specifically addressed bit and write the new byte back to the latch. These Read-Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of an external bipolar transistor cannot rise above the transistor’s base-emitter junction voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather than the pins returns the correct logic one value. Quasi Bi-directional Port Operation Port 1, Port 3 and Port 4 have fixed internal pull-ups and are referred to as ’quasi-bidi- rectional’ Ports. When configured as an input, the pin impedance appears as logic one and sources current in response to an external logic zero condition. Resets write logic one to all Port latches. If logical zero is subsequently written to a Port latch, it can be returned to input conditions by a logic one written to the latch. Note: Port latch values change near the end of Read-Modify-Write insruction cycles. Output buffers (and therefore the pin state) are updated early in the instruction after Read-Mod- ify-Write instruction cycle. Logical zero-to-one transitions in Port 1, Port 3 and Port 4 use an additional pull-up (p1) to aid this logic transition See Figure 2. This increases switch speed. This extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull-ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses logic zero and off when the gate senses logic one. pFET #1 is turned on for two oscillator periods immediately after a zero-to-one transition in the Port latch. A logic one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form a latch to drive logic one. pFET #2 is a very weak pull-up switched on whenever the Table 1. Read/Modify/Write Instructions Instruction Description Example ANL Logical AND ANL P1, A ORL Logical OR ORL P2, A XRL Logical EX-OR XRL P3, A JBC Jump if bit = 1 and clear bit JBC P1.1, LABEL CPL Complement bit CPL P3.0 INC Increment INC P2 DEC Decrement DEC P2 DJNZ Decrement and jump if not zero DJNZ P3, LABEL MOV Px.y, C Move carry bit to bit y of Port x MOV P1.5, C CLR Px.y Clear bit y of Port x CLR P2.4 SET Px.y Set bit y of Port x SET P3.3 |
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