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TSS463-AAR Datasheet(PDF) 10 Page - ATMEL Corporation

Part # TSS463-AAR
Description  VAN Data Link Controller with Serial Interface
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

TSS463-AAR Datasheet(HTML) 10 Page - ATMEL Corporation

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TSS463-AA
4205B–AUTO–12/04
The Slave Select signal must not toggle between each transmitted byte and therefore,
should be left at a low level during the whole SCI frame. SS must be asserted to inactive
high level at the end of the SCI frame.
If SS is not asserted, MISO pin is in high impedance state and incoming data is not
driven to the serial data register.
SCI Protocol
Same as the SPI protocol described earlier except for data arranging (LSB first and
MSB last).
Only 8 bits are monitored by the TSS463AA and master must
monitor
the
8
first
bits too (9th bit always equal to 1).
SCI Control Byte
Same as the SPI control byte.
Clocks and Speed
Considerations
SCLK and XTAL Clocks
The SPI/SCI speed rate is given by the CPU producing SCLK. XTAL clock controls the
speed rate on the VAN bus. The two clocks are asynchronous, but a minimum SPI/SCI
interframe spacing must be apply according to XTAL clock.
Intel and Motorola SPI Modes
Within an SPI byte, the maximum speed allowed on the MOSI line is 4 Mbits/s.
For example, when using a 1 MHz oscillator (sufficient to provide 62.5 kTS/s on the VAN
bus) the minimum inter-character delay is 12
µs (12 oscillator periods). Speed consider-
ations are detailed in Figure 7.
Figure 7. SPI Speed Considerations
SCI Mode
Within an SCI 9-bits data, the maximum speed allowed on the MOSI line is 125 Kbits/s.
When using a 1 MHz oscillator, the data transfer speed and the minimum delay time
between SCI bytes are shown on Figure 8.
SS
s at 1 MHz)
(4 s at 1 MHz)
(15 s at 1 MHz)
12 Xtal Min
8 Xtal Min
15 Xtal Min
4 Xtal Min
MOSI
Address
Control
SCLK
4 Mbits/s Max for SCLK
Data
(12 s at 1 MHz)
(8


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