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NLAST4051DR2 Datasheet(PDF) 1 Page - ON Semiconductor

Part # NLAST4051DR2
Description  Analog Multiplexer/ Demultiplexer
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NLAST4051DR2 Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2006
April, 2006 − Rev. 4
1
Publication Order Number:
NLAST4051/D
NLAST4051
Analog Multiplexer/
Demultiplexer
TTL Compatible, Single−Pole, 8−Position
Plus Common Off
The NLAST4051 is an improved version of the MC14051 and
MC74HC4051 fabricated in sub−micron Silicon Gate CMOS technology
for lower RDS(on) resistance and improved linearity with low current.
This device may be operated either with a single supply or dual supply up
to
±3 V to pass a 6 VPP signal without coupling capacitors.
When operating in single supply mode, it is only necessary to tie
VEE, pin 7 to ground. For dual supply operation, VEE is tied to a
negative voltage, not to exceed maximum ratings. Translation is
provided in the device, the Address and Inhibit are standard TTL level
compatible. For CMOS compatibility see NLAS4051. Pin for pin
compatible with all industry standard versions of ‘4051.’
Features
Improved RDS(on) Specifications
Pin for Pin Replacement for MAX4051 and MAX4051A
− One Half the Resistance Operating at 5.0 V
Single or Dual Supply Operation
− Single 3.0 − 5.0 V Operation, or Dual
±3 V Operation
− With VCC of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,
No Translators Needed
− Address and Inhibit Logic are Over−Voltage Tolerant and May Be
Driven Up +6 V Regardless of VCC
Address and Inhibit Pins Standard TTL Compatible
− Greatly Improved Noise Margin Over MAX4051 and MAX4051A
− True TTL Compatibility VIL = 0.8 V, VIH = 2.0 V
Improved Linearity Over Standard HC4051 Devices
Popular SOIC, and Space Saving TSSOP, and QSOP 16 Pin
Packages
Pb−Free Packages are Available*
Figure 1. Pin Connection
(Top View)
15
16
14
13
12
11
10
2
1
345
67
VCC
9
8
NO2
NO4
NO0
NO6 ADDC ADDB ADDA
NO1
NO3 COM
NO7
NO5 Inhibit VEE
GND
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
QSOP−16
QS SUFFIX
CASE 492
http://onsemi.com
MARKING
DIAGRAMS
TSSOP−16
DT SUFFIX
CASE 948F
SOIC−16
D SUFFIX
CASE 751B
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W
= Work Week
G
= Pb−Free Package
NLAST4051
AWLYWW
AST
4051
ALYW
G
G
(Note: Microdot may be in either location)
1
1
16
1
1
16
1
NLAST
4051
ALYW
1
16


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