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NLSF1174MNR2 Datasheet(PDF) 2 Page - ON Semiconductor |
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NLSF1174MNR2 Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 6 page NLSF1174 http://onsemi.com 2 Figure 2. LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 Q0 Q1 Q2 Q3 Q4 Q5 CLOCK RESET DATA INPUTS NONINVERTING OUTPUTS DESIGN/VALUE TABLE Design Criteria Value Unit Internal Gate Count* 40.5 ea Internal Gate Propagation Delay 1.5 ns Internal Gate Power Dissipation 5.0 mW Speed Power Product .0075 pJ *Equivalent to a two−input NAND gate. MAXIMUM RATINGS Parameter Symbol Value Unit DC Supply Voltage (Referenced to GND) VCC *0.5 to )7.0 V DC Input Voltage (Referenced to GND) VIN *1.5 to VCC )1.5 V DC Output Voltage (Referenced to GND) (Note 1) VOUT *0.5 to VCC )0.5 V DC Input Current, per Pin IIN $20 mA DC Output Current, per Pin IOUT $25 mA DC Supply Current, VCC and GND Pins ICC $50 mA Storage Temperature Range TSTG *65 to )150 °C Lead Temperature, 1 mm from Case for 10 Seconds PDIP, SOIC, TSSOP TL 260 °C Junction Temperature Under Bias TJ )150 °C Thermal Resistance QFN qJA 80 °C/W Power Dissipation in Still Air at 85 °C QFN PD 800 mW Moisture Sensitivity MSL Level 1 Flammability Rating Oxygen Index: 30 to 35 FR UL 94 V−0 @ 0.125 in ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) VESD u2000 u100 u500 V Latchup Performance Above VCC and Below GND at 85°C (Note 5) ILATCHUP $300 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. 6. For high frequency or heavy load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). |
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