NLSF1174MNR2G datasheet(3/6 Pages) ONSEMI

Part #	NLSF1174MNR2G

Description	Hex D Flip?묯lop with Common Clock and Reset

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NLSF1174

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RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Min

Max

Unit

DC Supply Voltage

(Referenced to GND)

VCC

2.0

6.0

V

DC Input Voltage, Output Voltage

(Referenced to GND) (Note 7)

VIN, VOUT

0

VCC

V

Operating Temperature, All Package Types

TA

*55

)125

°C

Input Rise and Fall Time (Figure 4)

VCC = 2.0 V

VCC = 4.5 V

VCC = 6.0 V

tr, tf

0

1000

500

400

ns

7. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Parameter

Test Conditions

VCC

V

Guaranteed Limit

Unit

Symbol

*555C to 255C

v855C

v1255C

Minimum High−Level Input Voltage

VOUT = 0.1 V or VCC – 0.1 V

|IOUT| v 20 mA

VIH

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

V

Maximum Low−Level Input Voltage

VOUT = 0.1 V or VCC – 0.1 V

|IOUT| v 20 mA

VIL

2.0

4.5

6.0

0.5

1.35

1.8

0.5

1.35

1.8

0.5

1.35

1.8

V

Minimum High−Level Output Voltage

VIN = VIH or VIL

|IOUT| v 20 mA

VOH

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

VIN = VIH or VIL

|IOUT| v 4.0 mA

|IOUT| v 5.2 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.7

5.2

Maximum Low−Level Output Voltage

VIN = VIH or VIL

|IOUT| v 20 mA

VOL

2.0

4.5

6.0

0.1

V

VIN = VIH or VIL

|IOUT| v 4.0 mA

|IOUT| v 5.2 mA

4.5

6.0

0.26

0.33

0.4

Maximum Input Leakage Current

VIN = VCC or GND

IIN

6.0

$0.1

$1.0

mA

Maximum Quiescent Supply Current

(per Package)

VIN = VCC or GND

IOUT = 0 mA

ICC

6.0

4.0

40

160

mA

8. Information on typical parametric values, along with high frequency or heavy load considerations, can be found in the ON Semiconductor

High−Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

Parameter

VCC

V

Guaranteed Limit

Unit

Symbol

*555C to 255C v855C

v1255C

Maximum Clock Frequency (50% Duty Cycle)

(Figures 4 and 7)

fmax

2.0

4.5

6.0

30

35

4.8

24

28

4.0

20

24

MHz

Maximum Propagation Delay, Clock to Q

(Figures 5 and 7)

tPLH

tPHL

2.0

4.5

6.0

110

22

19

140

28

24

165

33

28

ns

Maximum Propagation Delay, Reset to Q

(Figures 2 and 7)

tPLH

tPHL

2.0

4.5

6.0

110

21

19

140

28

24

160

32

27

ns

Maximum Output Transition Time, Any Output

(Figures 4 and 7)

tTLH

tTHL

2.0

4.5

6.0

75

15

13

95

19

16

110

22

19

ns

Maximum Input Capacitance

Cin

10

pF

Power Dissipation Capacitance, per Enabled Output (Note 10)

CPD

Typical @ 25

5C, VCC = 5.0 V

pF

62

9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed

CMOS Data Book (DL129/D).

10. Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see the ON

Semiconductor High−Speed CMOS Data Book (DL129/D).

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