SG3525ADWR2G datasheet(4/10 Pages) ONSEMI

Part #	SG3525ADWR2G

Description	Pulse Width Modulator Control Circuit

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Manufacturer	ONSEMI [ON Semiconductor]

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SG3525A

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ELECTRICAL CHARACTERISTICS (VCC = +20 Vdc, TA = Tlow to Thigh [Note 3], unless otherwise noted.)

Characteristics

Symbol

Min

Typ

Max

Unit

REFERENCE SECTION

Reference Output Voltage (TJ = +25°C)

Vref

5.00

5.10

5.20

Vdc

Line Regulation (+8.0 V

≤ VCC ≤ +35 V)

Regline

−

10

20

mV

Load Regulation (0 mA

≤ IL ≤ 20 mA)

Regload

−

20

50

mV

Temperature Stability

DVref/DT

−

20

−

mV

Total Output Variation Includes Line and Load Regulation over Temperature

DVref

4.95

−

5.25

Vdc

Short Circuit Current (Vref = 0 V, TJ = +25°C)

ISC

−

80

100

mA

Output Noise Voltage (10 Hz

≤ f ≤ 10 kHz, TJ = +25°C)

Vn

−

40

200

mVrms

Long Term Stability (TJ = +125°C) (Note 4)

S

−

20

50

mV/khr

OSCILLATOR SECTION (Note 5, unless otherwise noted.)

Initial Accuracy (TJ = +25°C)

−

±2.0

±6.0

%

Frequency Stability with Voltage

(+8.0 V

≤ VCC ≤ +35 V)

Dfosc

DVCC

−

±1.0

±2.0

%

Frequency Stability with Temperature

Dfosc

DT

−

±0.3

−

%

Minimum Frequency (RT = 150 kW, CT = 0.2 mF)

fmin

−

50

−

Hz

Maximum Frequency (RT = 2.0 kW, CT = 1.0 nF)

fmax

400

−

kHz

Current Mirror (IRT = 2.0 mA)

1.7

2.0

2.2

mA

Clock Amplitude

3.0

3.5

−

V

Clock Width (TJ = +25°C)

0.3

0.5

1.0

ms

Sync Threshold

1.2

2.0

2.8

V

Sync Input Current (Sync Voltage = +3.5 V)

−

1.0

2.5

mA

ERROR AMPLIFIER SECTION (VCM = +5.1 V)

Input Offset Voltage

VIO

−

2.0

10

mV

Input Bias Current

IIB

−

1.0

10

mA

Input Offset Current

IIO

−

1.0

mA

DC Open Loop Gain (RL ≥ 10 MW)

AVOL

60

75

−

dB

Low Level Output Voltage

VOL

−

0.2

0.5

V

High Level Output Voltage

VOH

3.8

5.6

−

V

Common Mode Rejection Ratio (+1.5 V

≤ VCM ≤ +5.2 V)

CMRR

60

75

−

dB

Power Supply Rejection Ratio (+8.0 V

≤ VCC ≤ +35 V)

PSRR

50

60

−

dB

PWM COMPARATOR SECTION

Minimum Duty Cycle

DCmin

−

0

%

Maximum Duty Cycle

DCmax

45

49

−

%

Input Threshold, Zero Duty Cycle (Note 5)

Vth

0.6

0.9

−

V

Input Threshold, Maximum Duty Cycle (Note 5)

Vth

−

3.3

3.6

V

Input Bias Current

IIB

−

0.05

1.0

mA

3. Tlow = 0°

Thigh = +70°C

4. Since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average

stability from lot to lot.

5. Tested at fosc = 40 kHz (RT = 3.6 kW, CT = 0.01 mF, RD = 0 W).

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