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UAA2016P Datasheet(PDF) 5 Page - ON Semiconductor

Part # UAA2016P
Description  Zero Voltage Switch Power Controller
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

UAA2016P Datasheet(HTML) 5 Page - ON Semiconductor

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UAA2016
http://onsemi.com
5
CIRCUIT FUNCTIONAL DESCRIPTION
Power Supply (Pin 5 and Pin 7)
The application uses a current source supplied by a single
high voltage rectifier in series with a power dropping
resistor. An integrated shunt regulator delivers a VEE
voltage of − 8.6 V with respect to Pin 7. The current used by
the total regulating system can be shared in four functional
blocks: IC supply, sensing bridge, triac gate firing pulses and
zener current. The integrated zener, as in any shunt
regulator, absorbs the excess supply current. The 50 Hz
pulsed supply current is smoothed by the large value
capacitor connected between Pins 5 and 7.
Temperature Sensing (Pin 3)
The actual temperature is sensed by a negative
temperature coefficient element connected in a resistor
divider fashion. This two element network is connected
between the ground terminal Pin 5 and the reference voltage
− 5.5 V available on Pin 1. The resulting voltage, a function
of the measured temperature, is applied to Pin 3 and
internally compared to a control voltage whose value
depends on several elements: Sawtooth, Temperature
Reduction and Hysteresis Adjust. (Refer to Application
Information.)
Temperature Reduction
For energy saving, a remotely programmable temperature
reduction is available on Pin 4. The choice of resistor R1
connected between Pin 4 and VCC sets the temperature
reduction level.
Comparator
When the noninverting input (Pin 3) receives a voltage
less than the internal reference value, the comparator allows
the triggering logic to deliver pulses to the triac gate. To
improve the noise immunity, the comparator has an
adjustable hysteresis. The external resistor R3 connected to
Pin 2 sets the hysteresis level. Setting Pin 2 open makes a
10 mV hysteresis level, corresponding to 0.15
°C. Maximum
hysteresis is obtained by connecting Pin 2 to VCC. In that
case the level is set at 5
°C. This configuration can be useful
for low temperature inertia systems.
Sawtooth Generator
In order to comply with European norms, the ON/OFF
period on the load must exceed 30 seconds. This is achieved
by an internal digital sawtooth which performs the
proportional regulation without any additional components.
The sawtooth signal is added to the reference applied to the
comparator inverting input. Figure 2 shows the regulation
improvement using the proportional band action. Figure 4
displays a timing diagram of typical system performance
using the UAA2016. The internal sawtooth generator runs
at a typical 40.96 sec period. The output duty cycle drive
waveform is adjusted depending on the time within the
40.96 sec period the drive needs to turn on. This occurs when
the voltage on the sawtooth waveform is above the voltage
provided at the Sense Input.
Noise Immunity
The noisy environment requires good immunity. Both the
voltage reference and the comparator hysteresis minimize
the noise effect on the comparator input. In addition the
effective triac triggering is enabled every 1/3 sec.
Failsafe
Output pulses are inhibited by the “failsafe” circuit if the
comparator input voltage exceeds the specified threshold
voltage. This would occur if the temperature sensor circuit
is open.
Sampling Full Wave Logic
Two consecutive zero−crossing trigger pulses are
generated at every positive mains half−cycle. This ensures
that the number of delivered pulses is even in every case. The
pulse length is selectable by Rsync connected on Pin 8. The
pulse is centered on the zero−crossing mains waveform.
Pulse Amplifier
The pulse amplifier circuit sinks current pulses from Pin
6 to VEE. The minimum amplitude is 70 mA. The triac is
then triggered in quadrants II and III. The effective output
current amplitude is given by the external resistor Rout.
Eventually, an LED can be inserted in series with the Triac
gate (see Figure 1).


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