1

SY10E142

SY100E142

Micrel, Inc.

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

s 700MHz min. shift frequency

s 9 bits wide for byte-parity applications

s Asynchronous Master Reset

s Dual clocks

s Fully compatible with industry standard 10KH,

100K ECL levels

s Internal 75K

s Fully compatible with Motorola MC10E/100E142

s Available in 28-pin PLCC package

FEATURES

9-BIT SHIFT

REGISTER

The SY10/100E142 are high-speed 9-bit shift registers

designed for use in new, high-performance ECL systems.

The E142 can accept serial or parallel data to be shifted out

in one direction as both serial and parallel outputs. The

accepts serial input data.

The SEL (Select) control pin serves to determine the

mode of operation, either SHIFT or LOAD. The shift direction

is from bit 0 to bit 8. The input data has to meet the set-up

time before being clocked into the nine input registers on

Reset) control signal asynchronously resets all nine

registers to a logic LOW when a logic HIGH is applied to

MR.

The E142 is designed for applications such as diagnostic

scan registers, parallel-to-serial conversions and is also

suitable for byte-wide parity.

DESCRIPTION

SY10E142

SY100E142

Rev.: E

Amendment: /0

Issue Date: March 2006

PIN NAMES

Pin

Function

Parallel Data Inputs

S-IN

Serial Data Input

SEL

Mode Select Input

Clock Inputs

MR

Master Reset

Data Outputs

BLOCK DIAGRAM

1

DQ

0

S-IN

SEL

MR

CLK1

CLK2

DQ

DQ

DQ

DQ

DQ

DQ

DQ

DQ

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0