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SY10E160

SY100E160

Micrel, Inc.

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

s Provides odd-HIGH parity of 12 inputs

s Output register with Shift/Hold capability

s 900ps max. D to Q, /Q output

s Enable control

s Asynchronous Register Reset

s Differential outputs

s Fully compatible with industry standard 10KH,

100K ECL levels

s Internal 75K

s Fully compatible with Motorola MC10E/100E160

s Available in 28-pin PLCC package

FEATURES

12-BIT PARITY

GENERATOR/CHECKER

The SY10/100E160 are high-speed, 12-bit parity

generator/checkers with differential outputs, for use in

new, high-performance ECL systems. The output Q takes

on a logic HIGH value only when an odd number of inputs

are at a logic HIGH. A logic HIGH on the enable input (EN)

forces the output Q to a logic LOW.

An additional feature of the E160 is the output register.

Two multiplexers and their associated signals control the

register input by providing the option of holding present

data, loading the new parity data or shifting external data

in. To hold the present data, the Hold signal (HOLD) must

be at a logic LOW level. If the HOLD signal is at a logic

HIGH, the data present at the Q output is passed through

the first multiplexer. Taking the Shift signal (SHIFT) to a

logic HIGH will shift the data at the S-IN pin into the output

register. If the SHIFT signal is at a logic LOW, the output

of the first multiplexer is then passed through to the register.

reset pin (R) forces the register output Y to a logic LOW.

DESCRIPTION

SY10E160

SY100E160

Rev.: F

Amendment: /0

Issue Date:

March 2006

BLOCK DIAGRAM

Q

Q

MUX

SEL

Y

Y

0

1

MUX

SEL

0

1

R

D

S-IN

SHIFT

R

EN

HOLD