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SY10E196JZTR Datasheet(PDF) 8 Page - Micrel Semiconductor |
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SY10E196JZTR Datasheet(HTML) 8 Page - Micrel Semiconductor |
8 / 10 page 8 Precison Edge® SY10E196 SY100E196 Micrel, Inc. M9999-032006 hbwhelp@micrel.com or (408) 955-1690 Typically, the analog input will be driven by an external DAC to provide a digital control with very fine analog output steps. The final resolution of the device will be dependent on the width of the DAC chosen. To determine the voltage range necessary for the FTUNE input, the graphs provided should be used. As an example, if a range of 40ps is selected to cover worst case conditions and ensure coverage of the digital range, from the 100E196 graph a voltage range of –3.25V to –4V would be necessary on the FTUNE pin. Obviously, there are numerous voltage ranges which can be used to cover a given delay range. Users are given the flexibility to determine which one best fits their design. Figure 1. Cascading Interconnect Architecture Cascading Multiple E196s To increase the programmable range of the E196, internal cascade circuitry has been included. This circuitry allows for the cascading of multiple E196s without the need for any external gating. Furthermore, this capability requires only one more address line per added E196. Obviously, cascading multiple PDCs will result in a larger programmable range; however, this increase is at the expense of a longer minimum delay. Figure 1 illustrates the interconnect scheme for cascading two E196s. As can be seen, this scheme can easily be expanded for larger E196 chains. The D7 input of the E196 is the cascade control pin. With the interconnect scheme of Figure 1, when D7 is asserted, it signals the need for a larger programmable range than is achievable with a single device. An expansion of the latch section of the block diagram is pictured below. Use of this diagram will simplify the explanation of how the cascade circuitry works. When D7 of chip #1 above is low, the cascade output will also be low, while the cascade bar output will be a logical high. In this condition, the SET MIN pin of chip #2 will be asserted and, thus, all of the latches of chip #2 will be reset and the device will be set at its minimum delay. Since the RESET and SET inputs of the latches are overriding, any changes on the A0–A6 address bus will not affect the operation of chip #2. Chip #1, on the other hand, will have both SET MIN and SET MAX de-asserted so that its delay will be controlled entirely by the address bus A0–A6. If the delay needed is greater than can be achieved with 31.75 gate Using the FTUNE Analog Input The analog FTUNE pin on the E196 device is intended to enhance the 20ps resolution capabilities of the fully digital E195. The level of resolution obtained is dependent on the number of increments applied to the appropriate range on the FTUNE pin. To provide another level of resolution, the FTUNE pin must be capable of adjusting the delay by greater than the 20ps digital resolution. As shown in the provided graphs, this requirement is easily achieved since a 100ps delay can be achieved over the entire FTUNE voltage range.This extra analog range ensures that the FTUNE pin will be capable, even under worst case conditions, of covering the digital resolution. E196 Chip #1 D1 D0 LEN VEE IN VBB IN VCC VCCO Q VCCO Q E196 Chip #2 D1 D0 LEN VEE IN VBB IN VCC VCCO Q VCCO Q ADDRESS BUS (A0 – A6) A7 Input Output LINEAR INPUT FTUNE FTUNE |
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