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SY10E256 Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY10E256 Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 4 page 1 SY10E256 SY100E256 Micrel, Inc. M9999-032206 hbwhelp@micrel.com or (408) 955-1690 s 950ps max. data to output s Extended 100E VEE range of –4.2V to –5.5V s 850ps max. latch enable to output s Separate select controls s Differential outputs s Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75K Ω input pulldown resistors s Fully compatible with Motorola MC10E/100E256 s Available in 28-pin PLCC package FEATURES 3-BIT 4:1 MUX-LATCH The SY10/100E256 offer three 4:1 multiplexers followed by latches with differential outputs designed for use in new, high-performance ECL systems. Separate Select controls are provided for the leading 2:1 mux pairs (see block diagram). When the Latch Enable (LEN) is at a logic LOW, the latch is transparent and output data is controlled by the multiplexer select controls. A logic HIGH on LEN latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. DESCRIPTION SY10E256 SY100E256 BLOCK DIAGRAM Pin Function D0x–D2x Parallel Data Inputs SEL1A, SEL1B First-stage Select Inputs SEL2 Second-stage Select Input LEN Latch Enable MR Master Reset Q0, Q0–Q2, Q2 Data Outputs VCCO VCC to Output PIN NAMES D R E N Q0 Q0 Q1 Q1 Q2 Q2 D R E N D R E N D0a SEL1B D0b D0c D0d D1a D1b D1c D1d D2a D2b D2c D2d SEL1A SEL2 LEN MR Rev.: G Amendment: /0 Issue Date: March 2006 |
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