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SY10E196

SY100E196

Micrel, Inc.

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

DESCRIPTION

FEATURES

PROGRAMMABLE DELAY

CHIP WITH ANALOG INPUT

SY10E196

SY100E196

s Up to 2ns delay range

s

s Linear input for tighter resolution

s >1GHz bandwidth

s On-chip cascade circuitry

s 75Kk

s Fully compatible with Motorola MC10E/100E196

s Available in 28-pin PLCC package

The SY10/100E196 are programmable delay chips

(PDCs) designed primarily for very accurate differential

ECL input edge placement applications.

The delay section consists of a chain of gates and a

linear ramp delay adjustment organized as shown in the

logic diagram. The first two delay elements feature gates

that have been modified to have delays 1.25 and 1.5

times the basic gate delay of approximately 80ps. These

two elements provide the E196 with a digitally-selectable

resolution of approximately 20ps. The required device

delay is selected by the seven address inputs D[0:6],

which are latched on-chip by a high signal on the latch

enable (LEN) control. If the LEN signal is either LOW or

left floating, then the latch is transparent.

The FTUNE input takes an analog coltage and applies

it to an internal linear ramp for reducing the 20s resolution

still further. The FTUNE input is what differentiates the

E196 from the E195.

An eighth latched input, D7, is provided for cascading

multiple PDCs for increased programmable range. The

cascade logic allows full control of multiple PDCs, at the

expense of only a single added line to the data bus for

each additional PDC, without the need for any external

gating.

Pin

Function

IN/IN

Signal Input

EN

Input Enable

D[0:7]

Mux Select Inputs

Q/Q

Signal Output

LEN

Latch Enable

SET MIN

Minimum Delay Set

SET MAX

Maximum Delay Set

CASCADE

Cascade Signal

FTUNE

Linear Voltage Input

PIN NAMES

Rev.: H

Amendment: /0

Issue Date:

March 2006