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A3250 Datasheet(PDF) 11 Page - Allegro MicroSystems |
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A3250 Datasheet(HTML) 11 Page - Allegro MicroSystems |
11 / 15 page Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches A3250 and A3251 11 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com VPH V+ t VPM VPL 0 Address 1 Address 2 Address n ( ≤ 63) Figure 5. Pulse sequence to select addresses Falling edge of final BOP address digit VPH V+ t VPM VPL 0 Encode Lock Bit Enable Address Blow 7 pulses 65 pulses Figure 6. Pulse sequence to encode lock bit Lock Bit Programming. After the desired BOP calibration value is programmed, and all of the corresponding bitfield-level fuses are blown, the device-level fuse should be blown. To do so, the lock bit (bitfield address 65) should be encoded as 1 and have its fuse blown. This is done in the same manner as permanently setting the other bitfields, as shown in figure 6. Address Selection . After addressing mode is enabled, the target bitfield address, is indicated by a series of VPM pulses, as shown in figure 3. When provisionally trying a value, this sequence is followed by a short VPH pulse, which serves to delimit the address and set the corresponding bitfield. When permanently setting a bitfield, the VPH pulse is continued for a longer period of time, suffienct to not only set the bitfield to 1, but also to blow the bitfield fuse. Enabling Addressing Mode . The first segment of code is a keying sequence used to enable the bitfield addressing mode. As shown in figure 4, this segment consists of one short VPH pulse, seven or more VPM pulses, and one short VPH pulse, with no supply interruptions. This sequence is designed to prevent the device from being programmed accidentally, such as by noise on the supply line. VPH V+ t VPM VPL 0 Minimum 7 pulses Figure 4. Addressing mode enable pulse sequence |
Similar Part No. - A3250_06 |
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Similar Description - A3250_06 |
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