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A3980KLPTR Datasheet(PDF) 10 Page - Allegro MicroSystems |
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A3980KLPTR Datasheet(HTML) 10 Page - Allegro MicroSystems |
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10 / 18 page  Automotive DMOS Microstepping Driver with Translator A3980 10 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Device Operation. The A3980 is a complete microstep- ping motor driver with a built-in translator for easy operation with minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, eighth-, and sixteenth-step modes. The currents in each of the two output full-bridges and all of the N-channel DMOS FETs are regulated with fixed off-time PMW (pulse width modulated) control cir- cuitry. At each step, the current for each full-bridge is set by the value of its external current-sense resistor (RS1 or RS2), a reference voltage (VREF), and the output voltage of its DAC (which in turn is controlled by the output of the translator). At power-up, the translator resets to the Home state, in which the motor is driven to the Home microstep position, where both phase currents are set to +70%. Then the translator sets the voltage regulator to mixed decay mode for both phases. When a step command signal occurs on the STEP input, the translator automatically sequences the DACs to the next level and current polarity. (See table 3 for the current-level sequence.) The microstep resolution is set by the combined effect of inputs MS1 and MS2, as shown in table 1. When stepping, if the new output levels of the DACs are lower than their previous output levels, then the decay mode (fast, slow, or mixed decay) for the active full-bridge is set by the PFD input. If the new output levels of the DACs are higher than or equal to their previous levels, then the decay mode for the active full-bridge is set to slow decay. This automatic current decay selection improves microstepping performance by reducing the distortion of the current wave- form that results from the back EMF of the motor. Home Microstep Position. At power-up, or after a UVLO (undervoltage lockout) condition caused by low voltage on VDD, the translator in the A3980 resets the motor to the Home microstep position. This corresponds to the 45° position, which is the step where both phase currents are +70%. Referring to table 3, for full-step mode this is step 1, for half-step this is step 2, for eighth-step this is step 5, and for sixteenth-step this is step 9. In table 3 and figures 5 through 8, the Home microstep position is indicated. Step Input (STEP). A low-to-high transition on the STEP input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the combined state of inputs MS1 and MS2. Microstep Select (MS1 and MS2). Selects the micro- stepping format, as shown in table 1. Any changes made to these inputs do not take effect until the next STEP rising edge. Direction Input (DIR). This determines the direction of rotation of the motor. When low, the direction will be clock- wise and when high, counterclockwise. Changes to this input do not take effect until the next STEP rising edge. Internal PWM Current Control. Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to a desired value, ITRIP. Initially, a diagonal pair of source and sink DMOS FETs are enabled and current flows through the motor winding and the current sense resistor, RS. When the voltage across RS equals the DAC output voltage, the current sense comparator resets the PWM latch. The latch then turns off either the source DMOS (when in slow decay mode) or the sink and source DMOSs (when in fast or mixed decay modes). The transconductance function is approximated by the maxi- mum value of current limiting, ITripMAX (A), which is set by ITripMAX = VREF ⁄ (8 ×R S) where RS is the resistance of the sense resistor (Ω) and VREF is the input voltage on the REF pin (V). The DAC output reduces the VREF output to the current sense comparator in precise steps, such that Itrip = (%ITripMAX ⁄ 100) × ITripMAX (See table 3 for %ITripMAX at each step.) It is critical that the maximum rating (0.5 V) on the SENSE pin is not exceeded. For full-step mode, VREF can be applied up to the maximum rating of VDD, because the peak sense value is 70% of maximum: VREF × (0.707 ⁄ 8) Functional Description |
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Similar Description - A3980KLPTR |
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