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SY10H603JC Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY10H603JC Datasheet(HTML) 1 Page - Micrel Semiconductor |
1 / 4 page 1 SY10H603 SY100H603 Micrel, Inc. M9999-032906 hbwhelp@micrel.com or (408) 955-1690 Pin Function GND TTL Ground (0V) VCCE ECL VCC (0V) VCCT TTL Supply (+5.0V) VEE ECL Supply (–5.2/–4.5V) D0–D8 Data Inputs (ECL) Q0–Q8 Data Outputs (TTL) OEECL 3-state Control (ECL) LEN Latch Enable (ECL) MR Master Reset (ECL) DESCRIPTION FEATURES s 9-bit ideal for byte-parity applications s 3-state TTL outputs s Flow-through configuration s Extra TTL and ECL power/ground pins to minimize switching noise s Dual supply s 6.0ns max. delay into 50pF, 12ns into 200pF (all outputs switching) s PNP TTL inputs for low loading s Choice of ECL compatibility: MECL 10KH (10Hxxx) or 100K (100Hxxx) s Fully compatible with MC10H/100H603 s Available in 28-pin PLCC package The SY10/100H603 are 9-bit, dual supply ECL-to-TTL translators. Devices in the Micrel 9-bit translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance. The devices feature a 48mA TTL output stage and AC performance is specified into both a 50pF and 200pF load capacitance. Latching is controlled by Latch Enable (LEN) and Master Reset (MR) resets the latches. A HIGH on OEECL sends the outputs into the high impedance state. All control inputs are ECL level. The 10H version is compatible with MECL 10KH ECL logic levels. The 100H version is compatible with 100K levels. SY10H603 SY100H603 9-BIT LATCHED ECL-TO-TTL Rev.: E Amendment: /0 Issue Date: March 2006 BLOCK DIAGRAM Q0 D0 ECL LEN MR TTL Q D EN Q1 D1 Q D EN Q2 D2 Q D EN Q3 D3 Q D EN Q4 D4 Q D EN Q5 D5 Q D EN Q6 D6 Q D EN Q7 D7 Q D EN Q8 D8 Q D EN OEECL PIN NAMES |
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