1

Micrel, Inc.

M9999-021407

hbwhelp@micrel.com or (408) 955-1690

SY100S811

FEATURES

DESCRIPTION

SY100S811

Rev.: H

Amendment: /0

Issue Date:

February 2007

SINGLE SUPPLY 1:9

PECL/TTL-TO-PECL

s PECL version of popular ECLinPS E111

s Low skew

s Guaranteed skew spec

s TTL enable input

s Selectable TTL or PECL clock input

s Single +5V supply

s Differential internal design

s Similar pin configuration to E111

s PECL I/O fully compatible with industry standard

s Internal 75K

s Available in 28-pin PLCC and SOIC packages

The SY100S811 is a low skew 1-to-9 PECL differential

driver designed for clock distribution in new, high-

performance PECL systems. It accepts either a PECL

When the TTL enable pin is HIGH, the TTL input is enabled

and the PECL input is disabled. When the enable pin is set

LOW, the TTL input is disabled and the PECL input is

enabled.

The device is specifically designed and produced for low

skew. The interconnect scheme and metal layout are

carefully optimized for minimal gate-to-gate skew within

the device. Wafer characterization and process control

ensure consistent distribution of propagation delay from lot

to lot. Since the S811 shares a common set of “basic”

processing with the other members of the ECLinPS family,

wafer characterization at the point of device personalization

allows for tighter control of parameters, including

propagation delay.

To ensure that the skew specification is met, it is

necessary that both sides of the differential output are

terminated into 50

Ω, even if only one side is being used. ln

most applications, all nine differential pairs will be used

and, therefore, terminated. In the case where fewer than

nine pairs are used, it is necessary to terminate at least the

output pairs on the same package side (i.e. sharing the

to maintain minimum skew.

voltage for single-ended reception of PECL signals to that

µF

capacitor.

BLOCK DIAGRAM

0

1

Precision Edge is a registered trademark of Micrel, Inc.