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AAT4618IGV-1.0-1-T1 Datasheet(PDF) 8 Page - Advanced Analog Technology, Inc. |
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AAT4618IGV-1.0-1-T1 Datasheet(HTML) 8 Page - Advanced Analog Technology, Inc. |
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8 / 11 page  AAT4618 Current Limited Load Switch 8 4618.2006.05.1.2 Applications Information Input Capacitor The input capacitor CIN protects the power supply from current transients generated by the load attached to the AAT4618. When a short circuit is suddenly applied to the output of the AAT4618, a large current, limited only by the RDS(ON) of the MOSFET, will flow for less than 1µs before the cur- rent limit circuitry activates. (See characteristic curve "Short Circuit Through 0.3 Ω.") In this event, a moderately sized CIN will dramatically reduce the voltage transient seen by the power supply and by other circuitry upstream from the AAT4618. The extremely fast short-circuit response time of the AAT4618 reduces the size requirement of CIN. CIN should be located as close to the device VIN pin as practically possible. Ceramic, tantalum, or alu- minum electrolytic capacitors are appropriate for CIN. There is no specific capacitor ESR requirement for CIN. However, for higher current operation, ceramic capacitors are recommended for CIN due to their inherent capability over tantalum capacitors to withstand input current surges from low impedance sources such as batteries in portable devices. Output Capacitor In order to insure stability while current limit is active, a low capacitance (approximately 0.47µF) is required. No matter how large the output capaci- tor, output current is limited to the value set by the AAT4618 current limiting circuitry, so very large output capacitors can be used. For example, USB ports are specified to have at least 120µF of capacitance downstream from their controlling power switch. The current limiting circuit will allow an output capacitance of 1000µF or more without disturbing the upstream power supply. ON (Enable Input) In many systems, power planes are controlled by integrated circuits which run at lower voltages than the power plane itself. The enable input (ON) of the AAT4618 has low and high threshold voltages that accommodate this condition. The threshold voltages are compatible with 5V TTL and 2.5V to 5V CMOS systems. When switching the AAT4618 on into a capacitive load, the AAT4618 will charge the output capacitive load at a rate no greater than the current limit setting. Attaching Loads Capacitive loads attached to an enabled AAT4618 will charge at a rate no greater than the current limit setting. FAULT Output The FAULT flag is provided to alert the system if an AAT4618 load is not receiving sufficient voltage to operate properly. If current limit or over-tempera- ture circuits in any combination are active for more than approximately 4ms, the FAULT flag is pulled to ground through approximately 100 Ω. The filter- ing of voltage or current transients of less than 4ms prevents capacitive loads connected to the AAT4618 output from activating the FAULT flag when they are initially attached. Pull-up resistanc- es of 1k Ω to 100kΩ are recommended. Since FAULT is an open drain terminal, it may be pulled up to any unrelated voltage less than the maximum operating voltage of 5.5V, allowing for level shifting between circuits. Thermal Considerations Since the AAT4618 has internal current limit and over-temperature protection, junction temperature is rarely a concern. However, if the application requires large currents in a hot environment, it is possible that temperature, rather than current limit, will be the dominant regulating condition. In these applications, the maximum current available with- out risk of an over-temperature condition must be calculated. The maximum internal temperature while current limit is not active can be calculated using Equation 1. Eq. 1: In Equation 1, IMAX is the maximum current required by the load. RDS(ON)(MAX) is the maximum rated RDS(ON) of the AAT4618 at high temperature. RθJA is the thermal resistance between the AAT4618 die and the board onto which it is mounted. TA(MAX) is the maximum temperature that the PCB under the T J(MAX) = IMAX 2 · R DS(ON)(MAX) · R ΘJA + TA(MAX) |
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