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AAT4625IKS-1-T1 Datasheet(PDF) 11 Page - Advanced Analog Technology, Inc. |
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AAT4625IKS-1-T1 Datasheet(HTML) 11 Page - Advanced Analog Technology, Inc. |
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11 / 15 page  Refer to the following guidelines for power port PCB layout: 1. PCB traces should be kept as short and direct as possible to minimize the effects of the PCB on circuit performance. 2. Make component solder pads large to mini- mize contact resistance. 3. The AAT4625 output bulk capacitor and ferrite beads should be placed as close to the device as possible. PCB traces to the output connec- tor should be kept as short as possible to min- imized trace resistance and the associated voltage drop (I2R loss). 4. If ferrite beads are used in the circuit, select fer- rite beads with a minimum series resistance. 5. The use of PCB trace vias should be avoided on all traces that conduct high currents. If vias are necessary, make the vias as large as pos- sible and use multiple vias connected in paral- lel to minimize their effect. AAT4625 USB Single-Channel Power Switch 4625.2006.04.1.2 11 Figure 3: Summary of Typical Circuit Voltage Drops Caused by AAT4625 Circuit Components and PCB Trace Resistance. Trace Resistance 0.01 Ω (5mV) (5mV) CBULK 0.1 μF CBULK 0.1 μF Cable, Connector, and Contact Resistance 0.03 Ω (15mV) (15mV) V+ GND Input Power Supply 4.50V to 5.25V P-Channel MOSFET Switch On Resistance 0.06 Ω (30mV) AAT4625 Ferrite Bead and PCB Trace Resistance 0.02 Ω (10mV) (10mV) VBUS GND Downstream Peripheral Port 500mA Max. Load Current Total Voltage Drop = 60mV Evaluation Board Layout The AAT4625 evaluation layout (shown in Figures 4, 5, and 6) follows the recommend printed circuit board layout procedures and can be used as an example for good application layouts. Note that ferrite beads are not used on this simple device evaluation board. The board layout shown is not to scale. Figure 4: Evaluation Board Figure 5: Evaluation Board Figure 6: Evaluation Board Component Side Layout. Solder Side Layout. Top Side Silk Screen Layout/ Assembly Drawing. |
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