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SY55856U Datasheet(PDF) 4 Page - Micrel Semiconductor |
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SY55856U Datasheet(HTML) 4 Page - Micrel Semiconductor |
4 / 9 page 4 SuperLite™ SY55856U Micrel, Inc. M9999-011207 hbwhelp@micrel.com or (408) 955-1690 FUNCTIONAL DESCRIPTION Establishing Static Logic Inputs The true pin of a CML input pair is internally biased to ground through a 75k Ω resistor. The complement pin of a CML input pair is internally biased halfway between V CC and ground by a voltage divider consisting of two 75k Ω resistors. To keep a CML input at static logic zero at V CC > 3.0V, leave both inputs unconnected. For V CC ≤ 3.0V, connect the complement input to V CC and leave the true input unconnected. To make an input static logic one, connect the true input to V CC, and leave the complement input unconnected. These are the only safe ways to cause CML inputs to be at a static value. In particular, no CML input should be directly connected to ground. All NC pins in the figures below should be left unconnected. VT (Variable Threshold) Inputs Five inputs to SY55856U, CINV, DELAY_SEL, S0, S1, and S2, are variable threshold inputs. The LVL input determines the Voltage threshold that differentiates logic high from logic low for these five inputs only. If LVL is left unconnected, the VT inputs will switch at about V GND 2 CC + or V TCL, whichever is higher. To obtain a logic switching threshold different from this, the LVL input must be driven with the actual desired threshold voltage. The user may drive the LVL pin with any voltage between V CC – 0.1V and ground. For example, driving LVL with a voltage set at Vcc – 1.3V causes the VT inputs to accept single ended PECL outputs and switch appropriately. Note that VT inputs are internally clamped so that the threshold will not fall below VTCL Volts. Since driving the LVL input to ground causes the threshold to be somewhere between V TCL (min) and VTCL (max), it is expected that the user will keep the Voltage at the LVL pin at or above V TCL (max). Please refer to Figure 3 for clarification. VCC NC IN /IN Figure 1. Hard Wiring a Logic "1"(1) NC VCC > 3.0V NC IN /IN NC VCC ≤ 3.0V VCC IN /IN Figure 2. Hard Wiring a Logic "0"(1) Operating Range VTCL VTCL VCC — 0.1V VCC — 0.1V VCC VCC LVL Input Logic Switching Threshold Figure 3a. Logic Switching Threshold 3 VCC 3.0V ≤ V CC ≤ 3.6V SY55856 909 Ω 1.10k S0, S1, S2 LVL TTL Driver VCC Figure 3b. Interfacing TTL-to-CML Select (CINV, DELAY_SEL, S0, S1, S2) Note 1. IN is either the DATA_IN or the CLK_IN input. /IN is either the / DATA_IN or the /CLK_IN input. |
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