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ATAM894X-TNSY Datasheet(PDF) 10 Page - ATMEL Corporation

Part # ATAM894X-TNSY
Description  8k-flash Microcontroller
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATAM894X-TNSY Datasheet(HTML) 10 Page - ATMEL Corporation

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4679D–4BMCU–05/05
ATAM894
5.2.8
Interrupt Processing
For processing the eight interrupt levels, the MARC4 includes an interrupt controller with two
8-bit wide “interrupt pending” and “interrupt active” registers. The interrupt controller samples all
interrupt requests during every non-I/O instruction cycle and latches these in the interrupt pend-
ing register. If no higher priority interrupt is present in the interrupt active register, it signals the
CPU to interrupt the current program execution. If the interrupt enable bit is set, the processor
enters an interrupt acknowledge cycle. During this cycle a short call (SCALL) instruction to the
service routine is executed and the current PC is saved on the return stack. An interrupt service
routine is completed with the RTI instruction. This instruction resets the corresponding bits in the
interrupt pending/active register and fetches the return address from the return stack to the pro-
gram counter. When the interrupt enable flag is reset (triggering of interrupt routines are
disabled), the execution of new interrupt service routines is inhibited but not the logging of the
interrupt requests in the interrupt pending register. The execution of the interrupt is delayed until
the interrupt enable flag is set again. Note that interrupts are only lost if an interrupt request
occurs while the corresponding bit in the pending register is still set (i.e., the interrupt service
routine is not yet finished).
5.2.9
Interrupt Latency
The interrupt latency is the time from the occurrence of the interrupt to the interrupt service rou-
tine being activated. In MARC4 this is extremely short (taking between 3 to 5 machine cycles
depending on the state of the core).
Figure 5-6.
Interrupt Handling
7
6
5
4
3
2
1
0
INT5 active
INT7 active
INT2 pending
SWI0
INT2 active
INT0 pending
INT0 active
INT2
RTI
RTI
INT5
INT3 active
INT3
RTI
RTI
RTI
INT7
Time
Main /
Autosleep
Main/
Autosleep


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