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U6808B-MFPG3Y Datasheet(PDF) 4 Page - ATMEL Corporation |
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U6808B-MFPG3Y Datasheet(HTML) 4 Page - ATMEL Corporation |
4 / 14 page 4 4707B–AUTO–10/05 U6808B 5. Description of the Watchdog Figure 5-1. Watchdog Block Diagram 5.1 Abstract The microcontroller is monitored by a digital window watchdog which accepts an incoming trig- ger signal of a constant frequency for correct operation. The frequency of the trigger signal can be varied in a broad range as the watchdog's time window is determined by external R/C compo- nents. The following description refers to the block diagram, see Figure 5-1. 5.2 WDI Input The microcontroller has to provide a trigger signal with the frequency f WDI which is fed to the WDI input. A positive edge of f WDI detected by a slope detector resets the binary counter and clocks the up/down counter additionally. The latter one counts only from 0 to 3 or reverse. Each correct trigger increments the up/down counter by 1, each wrong trigger decrements it by 1. As soon as the counter reaches status 3 the RS flip-flop is set (see Figure 5-2). A missing incoming trigger signal is detected after 250 clocks of the internal watchdog frequency f RC (see section “WD-OK Output”) and resets the up/down counter directly. 5.3 RCOSC Input With an external R/C circuitry the IC generates a time base (frequency f WDC) independent from the microcontroller. The watchdog's time window refers to a frequency of f WDC = 100 × fWDI 5.4 OSCERR Input A smart watchdog has to ensure that internal problems with its own time base are detected and do not lead to an undesired status of the complete system. If the RC oscillator stops oscillating a signal is fed to the OSCERR input after a time-out delay. It resets the up/down counter and dis- ables the WD-OK output. Without this reset function the watchdog would freeze in its current status when f RC stops. Slope detector Up/down counter Dual MUX Binary counter RS-FF RCOSC WDI RESET OSCERR WD-OK |
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