Micrel, Inc.

SY58626L

March 2006

5

M9999-030206-B

Pin Number

Pin Name

Pin Function

27, 28

TXLBQ,

/TXLBQ

Transmit loopback differential output: CML compatible output pair with 400mV swing

into a 50

Ω load (100Ω across the pair). The TXLBQ output pair is providing a copy of

the TXIN input signal, bypassing the pre-emphasis stage. The SY58626L loopback

function is optimized to operate with the SY58627L receiver, and the TXLBQ output

pair is AC-coupled directly to the TXLBIN input pair on the SY58627L.

23

/TXQSHDN

TXQ shutdown control pin: The TTL/CMOS (or VTH controlled) compatible pin is an

active LOW function. This input is internally connected to a 25kΩ pull-up resistor and

will default to a logic HIGH state if left open. When pulled LOW, the TXQ and /TXQ

output currents are shut off, and the TXQ and /TXQ output voltage is set to the same

potential. The actual voltage level is set by the resistor divider ratio established by

the internal 50

Ω source resistors (connected to VTTOUT) and the external load.

Default threshold is Vcc/2 when VTH pin is floating.

2

VTH

Input logic threshold control voltage for logic control threshold settings other than

LVTTL/CMOS. This input control pin can be externally biased to set the proper

threshold for all the logic control pins, /TXEN, LBSEL, /TXLBEN, 3-bit pre-emphasis

control, 2-bit pre-emphasis duration control, and /TXQSHDN. For standard

LVTTL/CMOS control, simply leave the VTH pin floating and the threshold voltage

21, 20

TXQ,

/TXQ

Differential variable swing output pair: This CML output pair is the output of the

the pair) with variable pre-emphasis. TXQ outputs include 50

Ω source termination

resistors. When the loopback mode is selected, the TXQ output pair is driven by the

RXLBIN inputs.

19, 22

VTTOUT

Output termination center-tap: Each side of the differential output pair terminates to

the VTTOUT pin through 50

Ω. The VTTOUT pin provides a center-tap to the output

termination network for maximum interface flexibility, and DC-offset capability.

Please refer to the “CML Output Interface Applications” section for more details.

17

18

32

MAG_CTRL0

MAG_CTRL1

MAG_CTRL2

Pre-emphasis magnitude level control input: TTL/CMOS (or VTH controlled)

compatible, 3-bit control interface. There are four levels of pre-emphasis magnitude,

as shown in the “Pre-Emphasis Magnitude Truth Table.” When MAG_CTRL2 (MSB)

is logic 1, pre-emphasis is disabled and the TXQ outputs will not include any pre-

emphasis. Pre-emphasis magnitude ranges from 10% to 33% above the base swing.

10

11

DUR_CTRL0

DUR_CTRL1

Pre-emphasis duration control input. TTL/CMOS (or VTH controlled) compatible, 2-bit

control interface. This control establishes the pre-emphasis duration. Duration ranges

from 60ps to 400ps typical as shown in the “Pre-emphasis Duration Control Truth

Table.” Pre-emphasis duration is measured from the mid-point of the pre-emphasis

magnitude (50% point). Please refer to the “Pre-emphasis Output Description” for

details.

9, 15, 26

VCC

Positive power supply: Connect to +3.3V power supply. Bypass with 0.1µF//0.01µF

low ESR capacitors as close to VCC pins as possible.

3, 6, 16, 25

VEE,

Exposed Pad

Ground: Ground pins and exposed pad must be connected to the same ground

plane.