Micrel, Inc.

SY87725L

February 2007

4

M9999-021607-A

Pin Description

RECEIVE SECTION SIGNALS

Pin Number

Pin Name

Pin Description

55, 56

SINP, SINN

Serial Data In (Differential LVPECL Input): This input receives the serial differential

data stream. An internal PLL recovers the embedded clock and data.

60, 61

REFCLKP,

REFCLKN,

Reference Clock (TTL or Differential LVPECL Input): This input accepts either single-

ended TTL or differential LVPECL signals and is used as the reference for the internal

frequency synthesizer and the “training” frequency for the receiver PLL to keep it

centered in the absence of data at the SIN input. The REFCLKN input has an internal

reference circuit that applies the threshold voltage in case of a single-ended TTL-

signal at REFCLKP. REFCLKN has an internal 75kΩ to GND and

can be left open

in that case.

15

REFFREQSEL

Reference Clock Frequency Select (TTL Input): Selects REFCLK frequency of

77.76MHz when LOW or 155.52MHz when HIGH.

6, 7

RCV_PLLRP,

RCV_PLLRN

Clock Recovery PLL Loop Filter: External loop filter pins for the receive PLL.

1, 2

RCV_PLLSN,

RCV_PLLSP

Clock Synthesis PLL Loop Filter: External loop filter pins for the clock synthesis PLL.

59

RCV_SYNC

Receive Synchronizer (TTL Input): Single-ended asynchronous input to set the word

boundary on the 4-bit parallel data

3, 5

RCV_FSEL0,

RCV_FSEL1

Receive Frequency Control (TTL Inputs): Two single-ended frequency selects for

receive synthesizer.

39, 40,

41, 42,

43, 44,

45, 46

DOUTOP, DOUT0N,

DOUT1P, DOUT1N,

DOUT2P, DOUT2N,

DOUT3P, DOUT3N

Parallel Data Out (LVDS Outputs): These are the four pairs of receive parallel data

outputs.

33, 34

CLKOUT2P,

CLKOUT2N

Parallel Clock Out (LVDS Output): This output is the recovered clock at the transmit

byte clock rate and provides a clock that can be used as a reference clock to drive

CLKIN.

36, 37

CLKOUTP,

CLKOUTN

Parallel Clock Out (LVDS Output): This output is the recovered clock divided by 4 or 8

to provide the parallel data rate clock.

18

LFIN

Link Fault Indicator (TTL Output): When HIGH, LFIN indicates CDR is “in-lock” and

when LOW it indicates CDR loss-of-lock.

63

RCV_DDRSEL

Double Data Rate Select (TTL Input): Selects either parallel data rate clock for normal

operation or one-half of parallel data rate clock for double data rate applications.

62

CD

Carrier Detect Input (LVPECL input): When HIGH, CD indicates the carrier is present

and when LOW it indicates the loss of carrier.

TRANSMIT SECTION SIGNALS

25, 26, 27,

28, 29, 30,

31, 32

DIN0P, DIN0N,

DIN1P, DIN1N,

DIN2P, DIN2N,

DIN3P, DIN3N

Parallel Data In (LVDS Inputs): These are the four pairs of transmit parallel data

inputs. Each Differential pair has a 100Ω internal termination across the pair.

22, 23

CLKINP, CLKINN

Parallel Clock In (LVDS Input): This input is the transmit parallel (byte-rate) clock.

10, 14

XMT_FSEL0,

XMT_FSEL1

Transmit Frequency Control (TTL Inputs): Two single-ended frequency selects for

transmit synthesizer.

11, 12

XMT_PLLSN,

XMT_PLLSP

Clock Synthesis PLL Loop Filter: External loop filter pins for the clock synthesis PLL.

49, 50

SOUTP, SOUTN

Serial Data Out (Differential CML Output): This is the serial differential data stream

output.

24

XMT_DDRSEL

Double Data Rate Select (TTL Input): Selects either parallel data rate clock for normal

operation or one-half of parallel data rate clock for double data rate applications.