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BCM8011 Datasheet(PDF) 1 Page - Broadcom Corporation. |
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BCM8011 Datasheet(HTML) 1 Page - Broadcom Corporation. |
1 / 2 page BCM8011 ® FOUR-CHANNEL 3.125 GIGABIT ETHERNET CMOS TRANSCEIVER Application Diagram • Support for four channels of 3.125 GigaBaud per second (GBd) resulting in an effective aggregate data rate of 10 Gigabits per second (Gbps) • Support for the 10 Gigabit attachment unit (XAUI) and 10 Gigabit media independent interface (XGMII) proposed by the IEEE 802.3ae standards • Less than 3 ps Root Mean Square (RMS) transmit jitter using Broadcom’s LC-VCO technology • 32 bytes of de-skewing capability for the channels • 32-bit parallel interface compatible to SSTL_2/HSTL (1.5) Class I EIA/JEDEC specifications • On-chip phase-locked loop (PLL), providing clock synthesis from 156.25 MHz clock references • Optional 8B/10B encoder and 10B/8B decoder in each channel • Parallel or serial loopback modes • Built-In Self-Test (BIST) capability • Termination resistors on-chip • Implemented in a 0.18µ standard CMOS process technology (1.8V and 2.5V supplies) • 2.5W nominal power • 324-pin FBGA package (19 mm x 19 mm) BCM8002 BCM8002 BCM8002 BCM8002 BCM8002 BCM8002 µP BCM5632 Switch Processor BCM8011 XAUI-XGMII Transceiver TBI XGMII XAUI Memory 1G Modules 10 GbE Backplane • Enables data transfer rate of 10 Gbps over metropolitan network when used with wavelength division multiplexing (WDM) or XAUI interface to a serial 10-Gbps laser module. • Ultra-low transmitter jitter on each channel results in a longer cable reach (in excess of 40 km). • EyeOpenerTM adaptive equalizer extends the speed and reach of copper traces over FR4 backplane. • Adaptive equalization and ultra-low receiver jitter enhance the receive eye pattern, which results in a superb bit-error rate (BER). • Easy-to-use programming of the global configuration registers facilitates the design of the system. It provides enable/disable functions such as PLL lock, channel synchronization, VCO bypass, serial and loopback modes for self-diagnosis, and selecting source-centered and source-synchronous clocking. • In-system at-speed link and on-board Built-In-Self-Test (BIST) is available using programmable pseudo-random bit sequence (PRBS) and programmable pattern comparators. FE A T UR E S SU MM AR Y O F B E N E FI TS |
Similar Part No. - BCM8011_04 |
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Similar Description - BCM8011_04 |
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