Micrel, Inc.

SY89464U

December 2005

M9999-120105-B

4

Pin Description

Pin Number

Pin Name

Pin Function

2, 5

7, 10

IN0, /IN0

IN1, /IN1

Differential Inputs: These input pairs are the differential signal inputs to the

device. These inputs accept AC- or DC-coupled signals as small as 100mV

Please refer to the “Input Interface Applications” section for more details.

4, 9

VREF-AC0

VREF-AC1

sink/source current is ±1.5mA. Please refer to the “Input Interface Applications”

section for more details.

3, 8

VT0, VT1

Input Termination Center-Tap: Each side of the differential input pair terminates

for maximum interface flexibility. Please refer to the “Input Interface Applications”

section for more details.

13, 15, 22, 23, 28

33, 34, 41, 43, 44

VCC

Positive Power Supply: Bypass with 0.1µF||0.01µF low ESR capacitors as close

40, 39

38, 37

36, 35

32, 31

30, 29

27, 26

25, 24

21, 20

19, 18

17, 16

Q0, /Q0

Q1, /Q1

Q2, /Q2

Q3, /Q3

Q4, /Q4

Q5, /Q5

Q6, /Q6

Q7, /Q7

Q8, /Q8

Q9, /Q9

Differential Outputs: These differential LVPECL outputs are a logic function of

the IN0, IN1, and SEL inputs. Please refer to the “Truth Table” below for details.

42

SEL

This single-ended TTL/CMOS-compatible input selects the inputs to the

multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor

1, 6, 11

GND,

Exposed Pad

Ground: Ground and exposed pad must be connected to the same ground

plane.

12

CAP

Power-On Reset (POR) initialization capacitor. When using the multiplexer with

internal RPE logic starts up in a known state. See “Power-On Reset (POR)

Description” section for more details regarding capacitor selection. If this pin is

function as a normal multiplexer. The CAP pin should never be left open or tied

directly to GND.

14

EN

Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q9

outputs. It is internally connected to a 25kΩ pull-up resistor and will default to a

logic HIGH state if left open. When disabled, CLK output goes LOW and /CLK

goes HIGH. EN being synchronous, outputs will be enabled/disabled when they

are in LOW state. Thus, a runt pulse is avoided if the device is enable/disabled

Truth Table

Inputs

Outputs

IN0

/IN0

IN1

/IN1

SEL

Q

/Q

0

1

X

X

0

0

1

1

0

X

X

0

1

0

X

X

0

1

1

0

1

X

X

1

0

1

1

0