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SY89533L Datasheet(PDF) 6 Page - Micrel Semiconductor |
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SY89533L Datasheet(HTML) 6 Page - Micrel Semiconductor |
6 / 16 page 6 Precision Edge® SY89536L Micrel, Inc. M9999-110405 hbwhelp@micrel.com or (408) 955-1690 V CC_LOGIC = VCCA/C = +3.3V ±10%, VCCOB = +1.8V ±10% Symbol Parameter Condition Min Typ Max Units fIN Reference Input Frequency 14 — 160 MHz fOUT Output Frequency Range 33.33 — 500 MHz tVCO Internal VCO Frequency Range 600 — 1000 MHz tskew Within Device Skew Within Bank PECL Note 9 —— 50 ps Within Bank HSTL Note 9 —— 75 ps Bank-to-Bank Note 9 — 60 150 ps Part-to-Part Skew Note 10 —— 200 ps tLOCK Maximum PLL Lock Time —— 10 ms tJITTER Cycle-to-Cycle Jitter (Pk-to-Pk) Note 11 —— 50 ps Period Jitter (rms) Note 12 —— 50 ps tpw (min) Minimum Pulse Width 50 —— ps Target PLL Loop Bandwidth Feedback Divider Ratio: 66 Note 13 — 1.0 — MHz Feedback Divider Ratio: 30 Note 13 — 2.0 — MHz tDC fOUT Duty Cycle 45 50 55 % tr, tf Output Rise/Fall Time (20% to 80%) LVPECL_Out — 250 400 ps HSTL_Out 100 — 400 ps tOUTPUT_RESET Note 14 —— 10 ns tHOLD_FSEL Note 14 5 —— ns tSETUP_FSEL Note 14 5 —— ns tOUTPUT_SYNC Note 14 1 —— VCO clock cycle FSEL-to-Valid Output Transition Time — 50 — ns tSETUP_OUT_SYNC 500 —— ps Note 8. All HSTL outputs loaded with 50 Ω to GND. Note 9. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. Note 10. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. Note 11. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC =Tn– Tn+1 where T is the time between rising edges of the output signal. Note 12. Period Jitter definition: For a specified amount of time (i.e., 1ms), there are N periods of a signal, and Tn is defined as the average period of that signal. Period jitter is defined as the variation in the period of the output signal for corresponding edges relative to Tn. Note 13. Using recommended loop filter components. Note 14. See “Timing Diagrams." AC ELECTRICAL CHARACTERISTICS |
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