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SY89538LHG Datasheet(PDF) 10 Page - Micrel Semiconductor

Part # SY89538LHG
Description  3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

SY89538LHG Datasheet(HTML) 10 Page - Micrel Semiconductor

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Micrel, Inc.
SY89538L
June 2006
M9999-062706-D
hbwhelp@micrel.com or (408) 955-1690
10
AC Electrical Characteristics
VCCA = VCCD = +3.3V ±10%; VCCO = +2.5V ±5% or +3.3V ±10%, RL (LVDS) = 100Ω across the output pairs, RL
(LVPECL) = 50Ω into VCCO–2V; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
XTAL Input Frequency Range
Note 7
14
18
MHz
Reference Input Frequency Range
See Table 8
9.325
756
MHz
fIN
Zero Delay Input Frequency Range
See Table 9
29.375
756
MHz
INSEL = LOW
9.325
94.5
MHz
fREF
Phase Detector Operating
Frequency Range
INSEL = HIGH
14
18
MHz
fOUT
Output Frequency Range
29.375
756
MHz
fVCO
Internal VCO Frequency Range
2352
3024
MHz
tSKEW
Output-to-Output
Note 8
15
75
ps
tLOCK
Minimum PLL Lock Time
10
ms
Loop Filter Optimized for Cycle-to-Cycle Jitter
• R = 50Ω
• C1 = 0.47µF
• C2 = 1000pF
Note 9
4
6
psRMS
Note 9
5
14
psRMS
Note 10
80
150
psPP
1-Sigma Cycle-to-Cycle Jitter (XTAL Input)
1-Sigma Cycle-to-Cycle Jitter (RFCK Reference)
Total Jitter
Spur
-35
dBc@
fphase
tJITTER
XTAL/RFCK Crosstalk-Induced Jitter
Note 11
0.7
psRMS
BW
PLL Bandwidth
See Table 10
14 ≤ fREF ≤ 18
11.1
38.4
kHz
tDC
FOUT Duty Cycle
43
50
57
%
tr, tf
Output Rise/Fall Time (20% to 80%)
LVPECL
100
250
400
ps
Output Rise/Fall Time (20% to 80%)
LVDS
80
150
300
ps
tPW_SYNC_MIN
Minimum SYNC Pulse Width
See “Synchronization”
section
8
Internal
clock
cycle
tPD_SYNC
Synchronization Delay
See “Synchronization”
section
8
Internal
clock
cycle
Notes:
7.
Fundamental mode, series resonant crystal.
8.
The output-to-output skew is defined as the worst-case difference between any outputs within a single device operating at the same voltage
and temperature.
9.
Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the
output signal.
10. Total jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10
12 output edges will deviate by more
than the specified peak-to-peak jitter value.
11. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each
other at the inputs.


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