8

SY89532/33L

Micrel, Inc.

M9999-110405

hbwhelp@micrel.com or (408) 955-1690

FUNCTIONAL DESCRIPTION

At the core of the SY89532/33L clock synthesizer is a

precision PLL driven by 14MHz to 18MHz series resonant

crystal. For users who wish to supply a TTL or LVPECL clock

input, please use the SY89534L or SY89535L. The PLL

output is sent to three banks of outputs. Each bank has its own

programmable frequency divider, and the design is optimized

to provide very low skew between banks, and very low jitter.

PLL Programming and Operation

IMPORTANT: If the internal VCO will be used, VCO_SEL

must be tied LOW, and ExtVCO pins can be left unconnected.

The internal VCO range is 600MHz to 1000MHz, and the

feedback ratio is selectable via the MSEL divider control (M3:0

pins). If the designer wishes to use the internal VCO, the

VCO_SEL pin must be tied low. The feedback ratio can be

changed without powering the chip down. The PLL output is

fed to three banks of outputs: Bank A, Bank B, and Bank C.

Banks A and C each have two differential LVPECL output

pairs. Bank B has nine differential output pairs. On the

SY89532L, Bank B is LVPECL. On the SY89533L, Bank B is

LVDS.

Each bank has a separate frequency divider circuit that can

be reprogrammed on the fly. The FSEL_x0:2 (where x is A,B,

or C) pins control the divider value. The FSEL divider can be

programmed in ratios from 2 to 18, and the outputs of Banks

A,B, and C can be synchronized after programming by pulsing

the OUT_SYNC pin HIGH-LOW-HIGH.

To determine the correct settings for SY89532/33L follow

these steps:

1. Refer to the "Suggested Selections for Specific

Customer Applications" section for common applications,

as well as the formula used to compute the output

frequency.

2. Determine the desired output frequency, such as

66MHz.

3. Choose a crystal frequency between 14MHz and 18MHz.

In this example, we choose 18MHz for the crystal

frequency. This results in an input/output ratio of 66/18.

4. Refer to the "Feedback Divide Select Table" and the

"Post-Divide Frequency Select Table" to find values for

MSEL and FSEL such that MSEL/FSEL equals the same

66/18 ratio. In this example, values of MSEL=44 and

FSEL=12 work.

5. Make sure that XTAL (the crystal frequency) multiplied

by MSEL is between 600MHz and 1000MHz.

The user may need to experiment with different crystal

frequencies to satisfy these requirements.

External VCO Operation

If the designer wishes to use an external VCO, the VCO_SEL

pin can be left floating or tied HIGH, and the external VCO

signal is connected to the ExtVCO differential input pair. The

ExtVCO input structure is designed to accept many popular

logic types. See “Input Interface for ExtVCO Pins” section for

interface diagrams. A SONET OC-48 compliant 622.08MHz

clock is a good example of an application requiring an external

VCO. For this application, use a VCXO to supply the

1244.16MHz. to the ExtVCO pins, and set VCO_SEL to HIGH.

To save power and reduce noise, the internal VCO is shut

down when VCO_SEL is HIGH.

ExtVCO Input Interface

The flexible ExtVCO inputs are designed to accept any

differential or single-ended input signal within 300mV above

Do not leave unused ExtVCO inputs floating. Tie either the

true or complement inputs to ground, but not both. A logic zero

is achieved by connecting the complement input to ground

with the true input floating. For a TTL input, tie a 2.5k

Ω resistor

between the complement input and ground. See “Input Interface

for ExtVCO Pins” section, Figures 5a through 5j.

Input Levels

LVDS, CML and HSTL differential signals may be connected

directly to the ExtVCO inputs. Depending on the actual worst

case voltage seen, the minimum input voltage swing varies as

illustrated in the following table:

Input Voltage Range

Minimum Voltage Swing

0 to 2.4V

100mV

200mV

R2

1.5k

R2

1.5k

R1

1.05k

R1

1.05k

GND

EXTVCO

/EXTVCO

Figure 1. Simplified Input Structure