SY89808L datasheet(4/8 Pages) MICREL | 3.3V, 500MHz, 1:9 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR

4 page

Precision Edge®

SY89808L

Micrel, Inc.

M9999-091405

hbwhelp@micrel.com or (408) 955-1690

AC ELECTRICAL CHARACTERISTICS

CCI = 3.3V ± 5%; VCCO = 1.8V ± 10%; All outputs are loaded with 50Ω to GND; TA = –40°C to +85°C, unless otherwise stated.

Symbol

Parameter

Condition

Min

Typ

Max

Units

MAX

Maximum Operating Frequency

OUT ≥ 450mV

500

——

MHz

Propagation Delay

CLK-to-Q

Note 3

0.800

1.000

1.200

SEL-to-Q

Note 3

0.800

1.200

1.700

SKEW

Within-Device Skew

Note 4

——

SKPP

Part-to-Part Skew

Note 5

——

400

Minimum Input Swing

Note 6

150

——

LVPECL_CLK

CMR

Common Mode Range

Note 7

–1.5

—–0.4

LVPECL_CLK

OE Set-Up Time

Note 8

1.0

——

OE Hold Time

0.5

——

r, tf

Output Rise/Fall Time (20% – 80%)

250

450

650

JITTER

Cycle-to-Cycle Jitter

Note 9

1ps

RMS

Total Jitter

Note 10

3. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential

output signals.

4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the

same voltage and temperature.

5. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same

voltage and temperature.

6. The V

PP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.

7. V

CMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The

numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or

equal to V

PP (min.). The lower end of the CMR range varies 1:1 with VCCI. The VCMR (min) will be fixed at 3.3V – |VCMR (min)|.

8. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures outputs remain disabled during the

next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock.

9. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T

n–Tn–1 where T is the time between rising edges of the

output signal.

10. Total jitter definition: with an ideal clock source of

≤ f

max, no more than one output edge in 10

12 output edges will deviate by more than the

specified amount.

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