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SY89825U

Micrel, Inc.

M9999-011907

hbwhelp@micrel.com or (408) 955-1690

FEATURES

• < 35ps max. ch-ch skew

The SY89825U is a High Performance Bus Clock Driver

with 22 differential LVPECL output pairs. This part is

designed for use in low voltage (2.5V, 3.3V) applications

which require a large number of outputs to drive precisely

aligned, ultra low skew signals to their destination. The

input is multiplexed from either LVDS or LVPECL by the

CLK_SEL pin. The LVDS input includes a 100

Ω internal

termination, thus eliminating the need for external

termination. The Output Enable (OE) is synchronous so

that the outputs will only be enabled/disabled when they

are already in the LOW state. This eliminates any chance

of generating a runt clock pulse when the device is enabled/

disabled as can happen with an asynchronous control.

The SY89825U features low pin-to-pin skew (35ps max.)

—performance previously unachievable in a standard

product having such a high number of outputs. The

SY89825U is available in a single space saving package

which provides a lower overall cost solution. In addition, a

single chip solution improves timing budgets by eliminating

the multiple device solution with their corresponding large

part-to-part skew.

2.5/3.3V 1:22 HIGH-PERFORMANCE,

LOW-VOLTAGE PECL BUS CLOCK DRIVER

& TRANSLATOR w/ INTERNAL TERMINATION

DESCRIPTION

SY89825U

APPLICATIONS

Rev.: D

Amendment: /0

Issue Date:

January 2007

Precision Edge is a registered trademark of Micrel, Inc.