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SY89834UMITR Datasheet(PDF) 4 Page - Micrel Semiconductor |
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SY89834UMITR Datasheet(HTML) 4 Page - Micrel Semiconductor |
4 / 10 page 4 Precision Edge® SY89834U Micrel, Inc. M9999-080505 hbwhelp@micrel.com or (408) 955-1690 V CC = 2.5V ±5% or VCC = 3.3V ±10% , RL = 50Ω to VCC–2V; TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units f MAX Maximum Frequency Input tr /tf ≥ 350ps 1.0 GHz t pd Propagation Delay IN-to-Q Note 6 200 320 500 ps t SW Switchover Time SEL-to-Q 200 320 500 ps t SKEW Within-Device Skew Note 7 5 20 ps Part-to-Part Skew Note 8 300 ps t JITTER Data Random Jitter (RJ) Note 9 1 ps RMS Deterministic Jitter (DJ) Note 10 10 ps PP Clock Cycle-to-Cycle Jitter Note 11 1 ps RMS Total Jitter (TJ) Note 12 10 ps PP DC Duty Cycle Input t r/tf ≥ 350ps, Note 13 45 50 55 % t S Set-Up Time EN to IN1, IN Note 14 and Note 15 300 ps t H Hold Time EN to IN1, IN Note 14 and Note 15 500 ps t r, tf Output Rise/Fall Times 70 140 225 ps (20% to 80%) Notes: 5. High-frequency AC parameters are guaranteed by design and characterization. 6. V IH = 2.0V, VIL = 0.8V, 50% duty cycle. Delay measured at 100MHz from the crossing of the input signal with VCC/2 as the crossing of the differential output signal. See Figure 1. 7. Within device skew is measured between two different outputs under identical input transitions. 8. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs. 9. Random jitter is measured with a K28.7 pattern, measured at ≤f MAX. 10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern. 11. Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs. T JITTER_CC = Tn – Tn+1, where T is the time between rising edges of the output signal. 12. Total jitter definition: with an ideal clock input frequency of ≤ f MAX (device), no more than one output edge in 10 12 output edges will deviate by more than the specified peak-to-peak jitter value. 13. If tr/tf is less than 350ps, the duty cycle distortion will increase beyond the duty cycle limits. 14. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications set-up and hold times do not apply. 15. See “Timing Diagrams,” Figure 1a. AC ELECTRICAL CHARACTERISTICS(5) |
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