Philips Semiconductors

Product specification

FBL2041

FBL2041I

3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)

1999 Apr 27

5

LOGIC DIAGRAM

SG00116

46

45

OEB0

OEB1

47

OEA1

BTL

Levels

TTL

Levels

TMS

TCK

TDI

TDO

42

44

22

21

(Future JTAG Boundary Scan option)

=

17, 49

LOGIC GND

=

1, 5, 7, 11, 13, 15, 19

=

23, 43

BUS GND

=

29, 31, 33, 35, 37, 39, 41

BIAS V

=

48

51

AI0

50

AO0

B0

40

25

OEB2

38

B1

20

2

52

OEA2

AI1

AO1

36

3

4

B2

AI2

AO2

34

8

6

B3

AI3

AO3

26

32

24

9

10

30

14

12

28

18

16

OEB3

B4

OEA3

AI4

AO4

B5

AI5

AO5

B6

AI6

AO6