January 1995

2

Philips Semiconductors

Product specification

4-bit synchronous decade counter with

asynchronous reset

HEF40160B

MSI

DESCRIPTION

The HEF40160B is a fully synchronous edge-triggered

4-bit decade counter with a clock input (CP), an overriding

asynchronous master reset (MR), four parallel data inputs

enable (PE), count enable parallel (CEP) and count enable

trickle (CET)), buffered outputs from all four bit positions

Operation is fully synchronous (except for the MR input)

and occurs on the LOW to HIGH transition of CP. When

PE is LOW, the next LOW to HIGH transition of CP loads

of CEP and CET inputs.

When PE is HIGH, the next LOW to HIGH transition of CP

advances the counter to its next state only if both CEP and

CET are HIGH; otherwise, no change occurs in the state

of the counter. TC is HIGH when the state of the counter is

LOW, independent of the state of all other inputs.

Multistage synchronous counting is possible without

additional components by using a carry look-ahead

counting technique; in this case, TC is used to enable

successive cascaded stages. CEP, CET and PE must be

stable only during the set-up time before the LOW to HIGH

transition of CP.

See Family Specifications

Fig.1 Functional diagram.