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HEF40195B Datasheet(PDF) 4 Page - NXP Semiconductors |
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HEF40195B Datasheet(HTML) 4 Page - NXP Semiconductors |
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4 / 8 page  January 1995 4 Philips Semiconductors Product specification 4-bit universal shift register HEF40195B MSI PINNING FUNCTION TABLE Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial 4. tn + 1 = state after next LOW to HIGH transition of CP PE parallel enable input (active LOW) P0 to P3 parallel data inputs J first stage J-input (active HIGH) K first stage K-input (active LOW) CP clock input (LOW to HIGH edge triggered) MR master reset input (active LOW) O0 to O3 buffered parallel outputs O3 buffered inverted output from last stage OPERATING MODE INPUTS (MR = HIGH) OUTPUTS AT tn + 1 PE J KP0 P1 P2 P3 O0 O1 O2 O3 O3 shift mode HL L X X X X L O0 O1 O2 O2 HL H X X X X O0 O0 O1 O2 O2 HH L X X X X O0 O0 O1 O2 O2 HH H X X X X H O0 O1 O2 O2 parallel entry mode LX X L L L L L L L L H LX X H H H H H H H H L |
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Similar Description - HEF40195B |
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