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CA3130AMZ Datasheet(PDF) 5 Page - Intersil Corporation |
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CA3130AMZ Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 17 page 5 Cascade-connected PMOS transistors Q2, Q4 are the constant-current source for the input stage. The biasing circuit for the constant-current source is subsequently described. The small diodes D5 through D8 provide gate-oxide protection against high-voltage transients, including static electricity during handling for Q6 and Q7. Second-Stage Most of the voltage gain in the CA3130 is provided by the second amplifier stage, consisting of bipolar transistor Q11 and its cascade-connected load resistance provided by PMOS transistors Q3 and Q5. The source of bias potentials for these PMOS transistors is subsequently described. Miller Effect compensation (roll-off) is accomplished by simply connecting a small capacitor between Terminals 1 and 8. A 47pF capacitor provides sufficient compensation for stable unity-gain operation in most applications. Bias-Source Circuit At total supply voltages, somewhat above 8.3V, resistor R2 and zener diode Z1 serve to establish a voltage of 8.3V across the series-connected circuit, consisting of resistor R1, diodes D1 through D4, and PMOS transistor Q1. A tap at the junction of resistor R1 and diode D4 provides a gate-bias potential of about 4.5V for PMOS transistors Q4 and Q5 with respect to Terminal 7. A potential of about 2.2V is developed across diode-connected PMOS transistor Q1 with respect to Terminal 7 to provide gate bias for PMOS transistors Q2 and Q3. It should be noted that Q1 is “mirror-connected (see Note 8)” to both Q2 and Q3. Since transistors Q1, Q2, Q3 are designed to be identical, the approximately 200 µA current in Q1 establishes a similar current in Q2 and Q3 as constant current sources for both the first and second amplifier stages, respectively. At total supply voltages somewhat less than 8.3V, zener diode Z1 becomes nonconductive and the potential, developed across series-connected R1, D1-D4, and Q1, varies directly with variations in supply voltage. Consequently, the gate bias for Q4, Q5 and Q2, Q3 varies in accordance with supply-voltage variations. This variation results in deterioration of the power-supply-rejection ratio (PSRR) at total supply voltages below 8.3V. Operation at total supply voltages below about 4.5V results in seriously degraded performance. Output Stage The output stage consists of a drain-loaded inverting amplifier using CMOS transistors operating in the Class A mode. When operating into very high resistance loads, the output can be swung within millivolts of either supply rail. Because the output stage is a drain-loaded amplifier, its gain is dependent upon the load impedance. The transfer characteristics of the output stage for a load returned to the negative supply rail are shown in Figure 2. Typical op amp loads are readily driven by the output stage. Because large- signal excursions are non-linear, requiring feedback for good waveform reproduction, transient delays may be encountered. As a voltage follower, the amplifier can achieve 0.01% accuracy levels, including the negative supply rail. NOTE: 8. For general information on the characteristics of CMOS transistor-pairs in linear-circuit applications, see File Number 619, data sheet on CA3600E “CMOS Transistor Array”. 3 2 7 4 8 1 5 6 BIAS CKT. COMPENSATION (WHEN REQUIRED) AV ≈ 5X AV ≈ AV ≈ 6000X 30X INPUT + - 200 µA 200 µA 1.35mA 8mA 0mA V+ OUTPUT V- STROBE CC OFFSET NULL CA3130 (NOTE 7) (NOTE 5) NOTES: 6. Total supply voltage (for indicated voltage gains) = 15V with input terminals biased so that Terminal 6 potential is +7.5V above Terminal 4. 7. Total supply voltage (for indicated voltage gains) = 15V with output terminal driven to either supply rail. FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES 22.5 GATE VOLTAGE (TERMINALS 4 AND 8) (V) 17.5 20 12.5 15 10 7.5 2.5 5 0 2.5 7.5 5 10 15 12.5 17.5 0 SUPPLY VOLTAGE: V+ = 15, V- = 0V TA = 25 oC LOAD RESISTANCE = 5k Ω 500 Ω 1k Ω 2k Ω FIGURE 2. VOLTAGE TRANSFER CHARACTERISTICS OF CMOS OUTPUT STAGE CA3130, CA3130A |
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