8

CONTROL REGISTER BIT ASSIGNMENT TABLE

BUS 7

BUS 6

BUS 5

BUS 4

BUS 3

BUS 2

BUS 1

BUS 0

B1

B0

OPERATION SELECT

REGISTER

RESET

0

0

No Operation

0

1

Multiply

1

0

Divide

1

1

Illegal State

B2 = 1, RESET Z REGISTER

B3 = 1, RESET Y REGISTER

B5

B4

NO. OF MDU’s

1

1

One MDU

1

0

Two MDU’s

0

1

Three MDU’s

0

0

Four MDU’s

NO. OF MDU’s

SHIFT RATE

1

Clock

÷ 2

B6 = 1, RESET SEQUENCE COUNTER

2

Clock

÷ 4

B7 = 1, SELECT SHIFT RATE OPTIONS:

B7 = 0, SHIFT = CLOCK FREQUENCY RATE

3

Clock

÷ 8

4

Clock

÷ 8

STATUS REGISTER

STATUS BYTE

BIT

76543

210

OUTPUT

00000

00

O.F.

NOTES:

1. O.F. = 1 if overflow (only valid after a divide has been done)

2. Bits 1 - 7 are read as 0 always.

DELAY NEEDED WITH AND WITHOUT PRESCALER

8N + 1 Shifts/Operation at 1 Clock Cycle/Shift

N = Number of MDU’s, S = Shift Rate

NO. OF MDU’s

WITHOUT PRESCALER

WITH PRESCALER

SHIFTS = 8N +1

NEEDED

(NOTE 1)

MACHINE CYCLES

NEEDED

SHIFTS = S (8N +1)

NEEDED

(NOTE 1)

MACHINE CYCLES

NEEDED

SHIFT RATE

1

9

2 (1 NOP)

18

3 (1 NOP)

2

2

17

2 (1 NOP)

68

9 (3 NOPs)

4

3

25

3 (1 NOP)

200

25 (9 NOPs)

8

4

33

4 (2 NOPs)

264

33 (11 NOPs)

8

NOTE:

1. NOP instruction is shown for machine cycles needed (3/NOP). Other instructions may be used.

CDP1855, CDP1855C