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OPA2107AUE4 Datasheet(PDF) 7 Page - Burr-Brown (TI) |
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OPA2107AUE4 Datasheet(HTML) 7 Page - Burr-Brown (TI) |
7 / 11 page OPA2107 7 SBOS161A www.ti.com FIGURE 2. FET Input Instrumentation Amplifier. I B = 5pA Max Gain = 100 CMRR ~ 95dB R IN = 10 13 Ω ~ Differential Voltage Gain = 1 + 2R F/RG = 100 A 1 Output 3 2 B 7 6 5 1 –In +In R F 5k Ω R F 5k Ω R G 101 Ω 25k Ω 25k Ω 1/2 OPA2107 1/2 OPA2107 25k Ω 25k Ω 6 5 3 2 INA105 FIGURE 3. Precision Instrumentation Amplifier. Using the INA106 for an output difference amplifier extends the input common-mode range of an instrumentation amplifier (IA) to ±10V. A conventional IA with a unity-gain difference amplifier has an input common-mode range limited to ±5V for an output swing of ±10V. This is because a unity-gain difference amplifier needs ±5V at the input for 10V at the output, allowing only 5V additional for common-mode range. E O = [10 (1 + 2RF /RG) (E2 – E1)] = 1000 (E2 – E1) A 1 E Output 3 2 B 7 6 5 1 E –In R F 10k Ω R F 10k Ω R G 202 Ω 10k Ω 10k Ω 1/2 OPA2107 1/2 OPA2107 100k Ω 100k Ω 6 5 3 2 INA106 1 O E +In 2 APPLICATIONS INFORMATION AND CIRCUITS The OPA2107 is unity-gain stable and has an excellent phase margin. This makes it easy to use in a wide variety of applications. Power-supply connections should be bypassed with capaci- tors positioned close to the amplifier pins. In most cases, 0.1 µF ceramic capacitors are adequate. Applications with larger load currents and fast transient signals may need up to 1 µF tantalum bypass capacitors. INPUT BIAS CURRENT The OPA2107 Difet input stages have very low input bias current—an order of magnitude lower than BIFET op amps. Circuit-board leakage paths can significantly degrade per- formance. This is especially evident with the SO-8 surface- mount package where pin-to-pin dimensions are particularly small. Residual soldering flux, dirt, and oils, which conduct leakage current, can be removed by proper cleaning. In most instances, a two-step cleaning process is adequate using a clean organic solvent rinse followed by deionized water. Each rinse should be followed by a 30-minute bake at 85 °C. A circuit-board guard pattern effectively reduces errors due to circuit-board leakage (Figure 1). By encircling critical high- impedance nodes with a low-impedance connection at the same circuit potential, any leakage currents will flow harm- lessly to the low-impedance node. Guard traces should be placed on all levels of a multiple-layer circuit board. A In Non-Inverting 1 A In Buffer 1 Out 2 3 A In Inverting 1 Out 2 3 Out 2 3 FIGURE 1. Connection of Input Guard. |
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