11

TM

Features

• Low Operating Current

• Industry Standard Pinout

• Two Chip-Select Inputs-Simple Memory Expansion

• Memory Retention for Standby Battery Voltage of 2V

Minimum

• Output-Disable for Common I/O Systems

• Three-State Data Output for Bus-Oriented Systems

• Separate Data Inputs and Outputs

Description

The CDP1822 and CDP1822C are 256-word by 4-bit static

random-access memories designed for use in memory sys-

tems where high speed, low operating current, and simplicity

in use are desirable. The CDP1822 features high speed and

a wide operating voltage range. Both types have separate

data inputs and outputs and utilize single power supplies of

4V to 6.5V for the CDP1822C and 4V to 10.5V for the

CDP1822.

Two Chip-Select inputs are provided to simplify system

expansion. An Output Disable control provides Wire-OR

capability and is also useful in common Input/Output sys-

tems. The Output Disable input allows these RAMs to be

used in common data Input/Output systems by forcing the

output into a high-impedance state during a write operation

independent of the Chip-Select input condition. The output

assumes a high-impedance state when the Output Disable is

at high level or when the chip is deselected by CS1 and/or

CS2.

The high noise immunity of the CMOS technology is pre-

served in this design. For TTL interfacing at 5V operation,

excellent system noise margin is preserved by using an

external pull-up resistor at each input.

Pinout

CDP1822, CDP1822C

(PDIP, SBDIP)

TOP VIEW

Ordering Information

5V

10V

PACKAGE

TEMP. RANGE

PKG.

NO.

CDP1822CE

CDP1822E

PDIP

E22.4

CDP1822CEX CDP1822EX

Burn-In

E22.4

CDP1822CD

CDP1822D

SBDIP

D22.4A

CDP1822CDX

-

Burn-In

D22.4A

1

11

10

9

8

7

6

5

3

2

4

22

12

13

14

15

16

17

18

19

21

20

A2

A1

A0

A5

A6

A7

DI1

DO1

DI2

A4

CS1

O. D.

CS2

R/W

DO4

DI4

DO3

DI3

DO2

A3

OPERATIONAL MODES

MODE

INPUTS

OUTPUT

CHIP

SELECT

1

CHIP

SELECT

2

OUTPUT

DISABLE

(OD)

READ/

WRITE

(R/W)

Read

0

1

0

1

Read

Write

0

1

0

0

Data In

Write

0

1

1

0

High

Imped-

ance

Standby

1

X

X

X

High

Imped-

ance

Standby

X

0

X

X

High

Imped-

ance

Output

Disable

XX

1

X

High

Imped-

ance

NOTE:

Logic 1 = High, Logic 0 = Low, X = Don’t Care.

March 1997

CDP1822,

CDP1822C

256-Word x 4-Bit

LSI Static RAM

File Number

1074.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Copyright © Intersil Americas Inc. 2001. All Rights Reserved