5

NOTES:

1. The holding register is loaded on the trailing edge of TPB.

3. Write is the overlap of TPB, CS1, and CS3 = 1 and CS3, RD/WR = 0

FIGURE 1. TRANSMITTER TIMING DIAGRAM - MODE 1

T CLOCK

THRE

WRITE (TPB)

SDO

12

1ST DATA BIT

TRANSMITTER SHIFT

REGISTER LOADED

(NOTE 2)

TRANSMITTER HOLDING

REGISTER LOADED

(NOTE 1)

34

5

6

7

14

15

16

1

23

4

(NOTE 3)

NOTES:

high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.

2. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0. If a pending DA has not been cleared by a read of the receiver holding register

by the time a new word is loaded into the receiver holding register, the OE signal will come true.

3. OE and PE share terminal 15 and are also available as two separate bits in the status register.

FIGURE 2. MODE 1 RECEIVER TIMING DIAGRAM

R CLOCK

READ

12

START BIT

CLOCK 7 1/2

SAMPLE

34

5

6

7

16

(NOTE 1)

SDI

12

34

5

6

7

8

9

STOP BIT 1

CLOCK 7 1/2 LOAD

HOLDING REGISTER

OE

PE

(NOTE 3)

FE

PARITY

DA

(NOTE 2)

TPB

(NOTE 3)

CDP1854A/3, CDP1854AC/3