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HSP45106JC-25 Datasheet(PDF) 3 Page - Intersil Corporation |
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HSP45106JC-25 Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 13 page 3 Functional Description The 16-bit Numerically Controlled Oscillator (NCO16) produces a digital complex sinusoid waveform whose frequency and phase are controlled through a standard microprocessor interface and discrete inputs. The NCO16 generates 16-bit sine and cosine vectors at a maximum sample rate of 33MHz. The NCO16 can be preprogrammed to produce a constant (CW) sine and cosine output for Direct Digital Synthesis (DDS) applications. Alternatively, the phase and frequency inputs can be updated in real time to produce a FM, PSK, FSK, or MSK modulated waveform. To simplify PSK generation, a 3 pin interface is provided to support modulation of up to 8 levels. As shown in Figure 1, the HSP45106 Block Diagram, the NCO16 is comprised of a Phase and Frequency Control Section (PFCS) and Sine/ Cosine Section. The PFCS stores the phase and frequency control inputs and uses them to calculate the phase angle of a rotating complex vector. The Sine/Cosine Section performs a lookup on this phase and generates the appropriate amplitude values for the sine and cosine. These quadrature outputs may be configured as serial or parallel with either two's complement or offset binary format. Phase/Frequency Control Section The phase and frequency of the quadrature outputs are controlled by the PFCS (Figure 1). The PFCS generates a 32-bit word which represents the instantaneous phase (Sin/Cos argument) of the sine and cosine waves being generated. This phase is incremented on the rising edge of each CLK by the preprogrammed amounts in the phase and Frequency Control Registers. As the instantaneous phase steps from 0 through full scale (232 - 1), the phase of the quadrature outputs proceeds from 0o around the unit circle counter clockwise. The PFCS is comprised of a Phase Accumulator Section, Phase Offset adder, Input Section, and a Timer Accumulator Section. The Phase Accumulator computes the instantaneous phase angle from user programmed values in the Center and Offset Frequency Registers. This angle is then fed into the Phase Offset adder where it is offset by the preprogrammed value in the Phase Offset Register. The Input Section routes data from a microprocessor compatible control bus and discrete input signals into the appropriate configuration registers. The Timer Accumulator supplies a pulse to mark the passage of a user programmed period of time. PMSEL I Phase Modulation Select input. Registered on chip by CLK. This input determines the source of the data clocked into the Phase Offset Register. When high, the Phase Input Register is selected. When low, the external modulation pins (MOD(2:1)) control the three most significant bits of the Phase Offset Register and the 13 least significant bits are set to zero. PACI I Phase Accumulator Carry Input (active low). Registered on chip by CLK. INITTAC I Initialize Timer Accumulator (active low). This input is registered on chip by CLK. When active, after being clocked onto chip, INITTAC enables the clocking of data into the Timer increment Register, and also zeroes the feedback path in the Timer Accumulator. TEST I Test Select Input. Registered on chip by CLK. This input is active high. When active, this input enables test busses to the outputs instead of the sine and cosine data. PAR/SER I Parallel/Serial Output Select. This input is registered on chip by CLK. When low, the sine and cosine outputs are in serial mode. The Output Shift Registers will load in new data after ENPHAC goes low and will start shifting the data out after ENPHAC goes high. When this input is high, the Output Registers are loaded every clock and no shifting takes place. BINFMT I Format. This input is registered on chip by CLK. When low, the MSB of the SIN and COS are inverted to form an offset binary (unsigned) number. OES I Three-state control for bits SIN(15:0). Outputs are enabled when OES is low. OEC I Three-state control for bits COS(15:0). Outputs are enabled when OEC is low. TICO O Timer Accumulator Carry Output. Active low, registered. This output goes low when a carry is generated by the Timer Accumulator. DACSTRB O DAC Strobe (active low). In serial mode, this output will go low when the first bit of a new output word is valid at the shift register output. This pin is active only in serial mode. SIN(15:0) O Sine Output Data. When parallel mode is enabled, data is output on SIN(15:0). When serial mode is enabled, output data bits are shifted out of SIN15 and SIN0. The bit stream on SIN15 is provided MSB first while the bit stream on SIN0 is provided LSB first. COS(15:0) O Cosine Output Data. When parallel mode is enabled, data is output on COS(15:0). When serial mode is enabled, output data bits are shifted out of COS15 and COS0. The bit stream on COS15 is provided MSB first while the bit stream in COS0 is provided LSB first. Index Pin Used to align chip in socket or on circuit board. Must be left as a no connect in circuit. (CPGA Package only). Pin Descriptions (Continued) NAME TYPE DESCRIPTION HSP45106 |
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