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7702AI Datasheet(PDF) 2 Page - Texas Instruments |
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7702AI Datasheet(HTML) 2 Page - Texas Instruments |
2 / 17 page TL7702A, TL7705A, TL7709A, TL7712A, TL7715A SUPPLY-VOLTAGE SUPERVISORS SLVS028H – APRIL 1983 – REVISED MAY 2003 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) The TL77xxA family of integrated-circuit supply-voltage supervisors is designed specifically for use as reset controllers in microcomputer and microprocessor systems. The supply-voltage supervisor monitors the supply for undervoltage conditions at the SENSE input. During power up, the RESET output becomes active (low) when VCC attains a value approaching 3.6 V. At this point (assuming that SENSE is above VIT+), the delay timer function activates a time delay, after which outputs RESET and RESET go inactive (high and low, respectively). When an undervoltage condition occurs during normal operation, RESET and RESET go active. To ensure that a complete reset occurs, the reset outputs remain active for a time delay after the voltage at the SENSE input exceeds the positive-going threshold value. The time delay is determined by the value of the external capacitor CT: td = 1.3 × 104 × CT, where CT is in farads (F) and td is in seconds (s). During power down and when SENSE is below VIT–, the outputs remain active until VCC falls below 2 V. After this, the outputs are undefined. An external capacitor (typically 0.1 µF) must be connected to REF to reduce the influence of fast transients in the supply voltage. functional block diagram The functional block diagram is shown for illustrative purposes only; the actual circuit includes a trimming network to adjust the reference voltage and sense-comparator trip point. RESIN ≈100 µA R1 (see Note A) 6 5 1 Reference Voltage SENSE GND 8 3 7 2 4 VCC CT REF NOTES: A. TL7702A: R1 = 0 Ω, R2 = open TL7705A: R1 = 7.8 k Ω, R2 = 10 kΩ TL7709A: R1 = 19.7 k Ω, R2 = 10 kΩ TL7712A: R1 = 32.7 k Ω, R2 = 10 kΩ TL7715A: R1 = 43.4 k Ω, R2 = 10 kΩ B. Resistor values shown are nominal. RESET RESET R2 (see Note A) |
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